{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,21]],"date-time":"2025-08-21T18:11:45Z","timestamp":1755799905146,"version":"3.44.0"},"reference-count":41,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,7,7]],"date-time":"2025-07-07T00:00:00Z","timestamp":1751846400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,7,7]],"date-time":"2025-07-07T00:00:00Z","timestamp":1751846400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,7,7]]},"DOI":"10.1109\/iolts65288.2025.11117086","type":"proceedings-article","created":{"date-parts":[[2025,8,19]],"date-time":"2025-08-19T18:07:28Z","timestamp":1755626848000},"page":"1-8","source":"Crossref","is-referenced-by-count":0,"title":["NAVIgator: Exploring the Voltage Limits of AMD NAVI GPUs for Energy Efficient Computing"],"prefix":"10.1109","author":[{"given":"Maria","family":"Trakosa","sequence":"first","affiliation":[{"name":"University of Athens,Greece"}]},{"given":"Odysseas","family":"Chatzopoulos","sequence":"additional","affiliation":[{"name":"University of Athens,Greece"}]},{"given":"George","family":"Papadimitriou","sequence":"additional","affiliation":[{"name":"University of Athens,Greece"}]},{"given":"Dimitris","family":"Gizopoulos","sequence":"additional","affiliation":[{"name":"University of Athens,Greece"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1049\/el:19740115"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830824"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00033"},{"key":"ref4","first-page":"503","article-title":"Harnessing voltage margins for energy effi-ciency in multicore cpus","volume-title":"2017 50th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)","author":"Papadimitriou","year":"2017"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2017.8046198"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00031"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD49847.2020.00012"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830811"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"volume-title":"PyTorch: an imperative style, high-performance deep learning library","year":"2019","author":"Paszke","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2019.8854386"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2020.2989813"},{"article-title":"Introducing rdna architecture: The all-new radeon gaming architecture powering \u201cnavi","volume-title":"AMD","year":"2019","key":"ref13"},{"issue":"5","key":"ref14","first-page":"14","volume":"20","author":"LeCun","year":"2015","journal-title":"Lenet-5, convolutional neural networks"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref17","article-title":"Learning multiple layers of features from tiny images","volume-title":"Technical Report","author":"Krizhevsky","year":"2009"},{"key":"ref18","article-title":"Very deep convolutional networks for large-scale image recognition","author":"Simonyan","year":"2014","journal-title":"arXiv preprint"},{"key":"ref19","first-page":"1097","article-title":"Imagenet classification with deep convolutional neural networks","author":"Krizhevsky","year":"2012","journal-title":"Advances in Neural Infor-mation Processing Systems (Ne u rIPS)"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/s11263-015-0816-y"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ICCV.2019.00140"},{"key":"ref22","first-page":"6105","article-title":"Efficientnet: Rethinking model scaling for convolutional neural networks","volume-title":"Proceedings of the International Conference on Machine Learning (ICML)","author":"Tan","year":"2019"},{"key":"ref23","article-title":"An image is worth 16\u00d716 words: Trans-formers for image recognition at scale","volume-title":"International Conference on Learning Representations (ICLR)","author":"Dosovitskiy","year":"2021"},{"key":"ref24","article-title":"Squeezenet: Alexnet-level accuracy with 50x fewer parameters and j 1mb model size","author":"Iandola","year":"2016","journal-title":"arXiv preprint"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICCV48922.2021.00986"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2017.243"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/cvpr.2018.00716"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.4324\/9781410605337-29"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2017.2742698"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.2992684"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.54"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2018.00043"},{"key":"ref33","first-page":"503","article-title":"Harnessing voltage margins for energy efficiency in multicore cpus","volume-title":"Proceedings of the 50th Annual IEEE\/ACM International Symposium on Microarchitecture, ser. MICRO-50 \u201917","author":"Papadimitriou","year":"2017"},{"key":"ref34","article-title":"A system-level voltage\/frequency scaling characterization framework for multi core cpus","author":"Papadimitriou","year":"2017","journal-title":"IEEE Silicon Errors in Logic - System Effects (SELSE 2017)"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/DSN-W.2018.00013"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2018.00014"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2017.8046198"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342175"},{"key":"ref39","first-page":"957","article-title":"Impact of voltage scaling on soft errors susceptibility of multicore server cpus","volume-title":"Proceedings of the 56th Annual IEEE\/ACM International Symposium on Microarchitecture, ser. MICRO \u201923","author":"Agiakatsikas","year":"2023"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2024.3500366"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056030"}],"event":{"name":"2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS)","start":{"date-parts":[[2025,7,7]]},"location":"Ischia, Italy","end":{"date-parts":[[2025,7,9]]}},"container-title":["2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11115077\/11116814\/11117086.pdf?arnumber=11117086","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,20]],"date-time":"2025-08-20T06:20:27Z","timestamp":1755670827000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11117086\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,7,7]]},"references-count":41,"URL":"https:\/\/doi.org\/10.1109\/iolts65288.2025.11117086","relation":{},"subject":[],"published":{"date-parts":[[2025,7,7]]}}}