{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T17:08:34Z","timestamp":1760202514797,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2002]]},"DOI":"10.1109\/ipdps.2002.1016547","type":"proceedings-article","created":{"date-parts":[[2005,8,24]],"date-time":"2005-08-24T23:23:34Z","timestamp":1124925814000},"page":"8 pp","source":"Crossref","is-referenced-by-count":6,"title":["On the communication capability of the self-reconfigurable gate array architecture"],"prefix":"10.1109","author":[{"given":"H.M.","family":"El-Boghdadi","sequence":"first","affiliation":[]},{"given":"R.","family":"Vaidyanathan","sequence":"additional","affiliation":[]},{"given":"J.L.","family":"Trahan","sequence":"additional","affiliation":[]},{"given":"S.","family":"Rai","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-540-48302-1_31","article-title":"Genetic Programming using Self-Reconfigurable FPGAs","author":"sidhu","year":"1999","journal-title":"Int Workshop on Field Programmable Logic and Applications"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296463"},{"key":"ref12","first-page":"106","article-title":"A Self-Reconfigurable Gate Array Architecture","volume":"1896","author":"sidhu","year":"2000","journal-title":"Int Conf on Field Programmable Logic and Applications"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1006\/jpdc.1996.0047"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1117\/12.221328"},{"key":"ref4","article-title":"Hardware Object Selection for Mapping Loops onto Reconfigurable Architectures","author":"bondalapati","year":"1999","journal-title":"Proc Ini'l Conf Par and Distr Processing Techniques and Applic"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1006\/inco.1995.1122"},{"key":"ref6","article-title":"A Bit Model of Reconfigurable Mesh","author":"jang","year":"1994","journal-title":"Ptoc 1st Reconfiqurable Arch Workshop"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-64359-1_675"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1142\/S0129626495000102"},{"journal-title":"Introduction to Parallel Algorithms and Architectures Arrays· Trees· Hypercubes","year":"1992","author":"leighton","key":"ref7"},{"journal-title":"Configuration Guide","article-title":"AT6000 Series Configuration","year":"1997","key":"ref2"},{"journal-title":"Discrete Mathematics with Combinatorics","year":"2001","author":"anderson","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-64359-1_676"}],"event":{"name":"Proceedings 16th International Parallel and Distributed Processing Symposium. IPDPS 2002","start":{"date-parts":[[2001,4,15]]},"location":"Ft. Lauderdale, FL","end":{"date-parts":[[2001,4,19]]}},"container-title":["Proceedings 16th International Parallel and Distributed Processing Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/7926\/21854\/01016547.pdf?arnumber=1016547","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T18:55:11Z","timestamp":1497639311000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1016547\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/ipdps.2002.1016547","relation":{},"subject":[],"published":{"date-parts":[[2002]]}}}