{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T18:48:25Z","timestamp":1729622905656,"version":"3.28.0"},"reference-count":18,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/ipdps.2003.1213292","type":"proceedings-article","created":{"date-parts":[[2004,3,22]],"date-time":"2004-03-22T09:34:28Z","timestamp":1079948068000},"page":"8","source":"Crossref","is-referenced-by-count":1,"title":["PROSIDIS: a special purpose processor for protein similarity discovery"],"prefix":"10.1109","author":[{"given":"A.","family":"Marongiu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Palazzari","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V.","family":"Rosato","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"OPERA: A Toolbox for Loop Parallelization","author":"loechner","year":"0","journal-title":"2nd Int l Workshop Software Eng for Parallel and Distributed Systems"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45492-6_33"},{"key":"ref12","article-title":"Optimization of Automatically Generated Parallel Programs","author":"marongiu","year":"0","journal-title":"Proc of the 3rd IMACS International Multiconference CSCC'99"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"51","DOI":"10.1023\/A:1008012332212","article-title":"A Systolic Design Methodology with Application to Full-Search Block-Matching Architectures","volume":"19","author":"chen","year":"1998","journal-title":"J of VLSI Signal Proc"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.1990.145495"},{"key":"ref15","first-page":"141","article-title":"Efficient Systolic Arrays for FFT Algorithms","author":"lim","year":"0"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/92.736145"},{"journal-title":"Optimisation for the automatic synthesis of digital circuits","year":"2001","author":"deodati","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1073\/pnas.89.22.10915"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1006\/jmbi.1990.9999"},{"key":"ref3","article-title":"Configurable Computing: A Survey of Systems and Software","author":"compton","year":"1999","journal-title":"Northwestern University Dept of ECE Technical Report"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/32.842951"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/S0010-4655(01)00234-X"},{"journal-title":"IEEE Standard VHDL Language Reference Manual IEEE Std","first-page":"1076","year":"0","key":"ref8"},{"article-title":"Hardware and Software High Level Synthesis of Affine Iterative Algorithms","year":"2000","author":"marongiu","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707890"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707878"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/BF01192158"}],"event":{"name":"International Parallel and Distributed Processing Symposium (IPDPS 2003)","acronym":"IPDPS-03","location":"Nice, France"},"container-title":["Proceedings International Parallel and Distributed Processing Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8608\/27277\/01213292.pdf?arnumber=1213292","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T00:26:05Z","timestamp":1497572765000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1213292\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/ipdps.2003.1213292","relation":{},"subject":[]}}