{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T06:21:06Z","timestamp":1730269266245,"version":"3.28.0"},"reference-count":9,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/ipdps.2003.1213343","type":"proceedings-article","created":{"date-parts":[[2004,3,22]],"date-time":"2004-03-22T09:34:28Z","timestamp":1079948068000},"page":"7","source":"Crossref","is-referenced-by-count":9,"title":["Efficient FPGA implementation of block cipher MISTY1"],"prefix":"10.1109","author":[{"given":"G.","family":"Rouvroy","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"F.-X.","family":"Standaert","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.-J.","family":"Quisquater","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.-D.","family":"Legat","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","article-title":"An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists","author":"elbirt","year":"0","journal-title":"The Third Advanced Encryption Standard (AES3) Candidate Conference"},{"journal-title":"Supporting Document of MISTY1","year":"0","author":"matsui","key":"ref3"},{"first-page":"13","year":"2000","author":"gaj","key":"ref6"},{"key":"ref5","first-page":"65","article-title":"High Performance Single Ship FPGA Rijndael Algorithm Implementations","author":"mcloone","year":"0","journal-title":"Proc of CHES2001 The Third International CHES Workshop Lecture Notes In Computer Science LNCS2162"},{"key":"ref8","article-title":"Efficient Uses of FPGAs for Implementations of DES and Its Experimental Linear Crypt-analysis","volume":"52","author":"rouvroy","year":"2003","journal-title":"Accepted for publication in IEEE Transactions on Computers Special CHES Edition"},{"key":"ref7","article-title":"Efficient FPGA Implementations of Block Ciphers KHAZAD and MISTY1","author":"standaert","year":"0","journal-title":"Proc Third NESSIE Workshop"},{"key":"ref2","article-title":"New Block Encryption Algorithm MIST Y","author":"matsui","year":"1997","journal-title":"Proc of FSE'97 LNCS Springer"},{"key":"ref9","article-title":"Methodology to Implement Block Ciphers in Reconfigurable Hardware and its Application to Fast and Compact AES Rijndael","author":"standaert","year":"2003","journal-title":"Accepted for publication in the proceedings of FPGA"},{"journal-title":"Xilinx Virtex 2 5V field programmable gate arrays data sheet","year":"0","key":"ref1"}],"event":{"name":"International Parallel and Distributed Processing Symposium (IPDPS 2003)","acronym":"IPDPS-03","location":"Nice, France"},"container-title":["Proceedings International Parallel and Distributed Processing Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8608\/27277\/01213343.pdf?arnumber=1213343","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T15:05:50Z","timestamp":1489417550000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1213343\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/ipdps.2003.1213343","relation":{},"subject":[]}}