{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T18:34:43Z","timestamp":1729622083158,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/ipdps.2004.1303101","type":"proceedings-article","created":{"date-parts":[[2004,6,10]],"date-time":"2004-06-10T14:19:45Z","timestamp":1086877185000},"page":"132-139","source":"Crossref","is-referenced-by-count":17,"title":["A parallel architecture for secure FPGA symmetric encryption"],"prefix":"10.1109","author":[{"given":"E.J.","family":"Swankoski","sequence":"first","affiliation":[]},{"given":"R.R.","family":"Brooks","sequence":"additional","affiliation":[]},{"given":"V.","family":"Narayanan","sequence":"additional","affiliation":[]},{"given":"M.","family":"Kandemir","sequence":"additional","affiliation":[]},{"given":"M.J.","family":"Irwin","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"crossref","DOI":"10.1145\/586110.586132","article-title":"Silicon physical random functions","author":"gassend","year":"2002","journal-title":"Proceedings of the Computer and Communication Security Conference"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253591"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2001.941144"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1049\/el:20030746"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.2000.903398"},{"key":"1","first-page":"207","article-title":"A fully pipelined memoryless 17.8 Gbps AES-128 encryptor","author":"jarvinen","year":"0","journal-title":"Proceedings of the 2003 ACM\/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays"},{"key":"10","article-title":"Advanced encryption standard","volume":"197","year":"2001","journal-title":"Federal Information Processing Standards Publication"},{"journal-title":"Applied Cryptography Second Edition","year":"1996","author":"schneier","key":"7"},{"journal-title":"Field Programmable Gate Arrays Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems","year":"1995","author":"oldfield","key":"6"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2002.1030728"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/360276.360309"},{"key":"9","article-title":"AES proposal: Rijndael","author":"daemen","year":"1999","journal-title":"AES Algorithm Submission"},{"key":"8","article-title":"Data encryption standard","volume":"46","year":"1993","journal-title":"Federal Information Processing Standards Publication"}],"event":{"name":"18th International Parallel and Distributed Processing Symposium, 2004.","location":"Santa Fe, NM, USA"},"container-title":["18th International Parallel and Distributed Processing Symposium, 2004. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9132\/28950\/01303101.pdf?arnumber=1303101","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,13]],"date-time":"2024-01-13T16:39:44Z","timestamp":1705163984000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1303101\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/ipdps.2004.1303101","relation":{},"subject":[]}}