{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T04:30:07Z","timestamp":1729657807973,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/ipdps.2004.1303107","type":"proceedings-article","created":{"date-parts":[[2004,6,10]],"date-time":"2004-06-10T14:19:45Z","timestamp":1086877185000},"page":"135-142","source":"Crossref","is-referenced-by-count":3,"title":["Models and reconfiguration problems for multi task hyperreconfigurable architectures"],"prefix":"10.1109","author":[{"given":"S.","family":"Lange","sequence":"first","affiliation":[]},{"given":"M.","family":"Middendorf","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","article-title":"Compile-time optimization of dynamic hardware reconfigurations","author":"teich","year":"1999","journal-title":"Proc Int Conf on Par and Distr Proc Techniques and Appl (PDPTA'99)"},{"key":"16","first-page":"443","article-title":"Efficient self-reconfigurable implementations using on-chip memory","author":"wadhwa","year":"2000","journal-title":"Proc FPL"},{"key":"13","first-page":"106","article-title":"A self-reconfigurable gate array architecture","author":"sidhu","year":"2000","journal-title":"Proc FPL"},{"doi-asserted-by":"publisher","key":"14","DOI":"10.1109\/ICCAD.2001.968609"},{"key":"11","first-page":"296","article-title":"Dynamic runtime re-scheduling allowing multiple implementations of a task for platform-based designs","author":"lee","year":"2002","journal-title":"Proc 2002 Conf Design Automation and Test in Europe"},{"key":"12","article-title":"Models and architectures for hyperreconfigurable hardware","volume":"1148","author":"middendorf","year":"2003","journal-title":"1st Meeting DFG Priority Programme"},{"doi-asserted-by":"publisher","key":"3","DOI":"10.1145\/360276.360342"},{"doi-asserted-by":"publisher","key":"2","DOI":"10.1145\/508352.508353"},{"key":"1","article-title":"Reconfigurable computing: Architectures, models and algorithms","author":"bondalapati","year":"1997","journal-title":"Proc Reconfigurable Architectures Workshop"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1145\/503048.503078"},{"key":"7","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1109\/DAC.2002.1012596","article-title":"On metrics for comparing routability estimation methods for FP-GAs","author":"kannan","year":"2002","journal-title":"Proc 39th Design Autom Conf"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1109\/43.775631"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1109\/DATE.2002.998399"},{"key":"4","first-page":"248","article-title":"Routing on switch matrix multi-FPGA-systems","author":"ejnioui","year":"2000","journal-title":"13th International Conference on VLSI Design"},{"year":"2003","author":"lange","journal-title":"Hyperreconfigurable Architectures and the Partition into Hypercontexts Problem","key":"9"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/DATE.2002.998356"}],"event":{"name":"18th International Parallel and Distributed Processing Symposium, 2004.","location":"Santa Fe, NM, USA"},"container-title":["18th International Parallel and Distributed Processing Symposium, 2004. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9132\/28950\/01303107.pdf?arnumber=1303107","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T07:57:42Z","timestamp":1497599862000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1303107\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/ipdps.2004.1303107","relation":{},"subject":[]}}