{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T18:02:52Z","timestamp":1729620172868,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/ipdps.2004.1303117","type":"proceedings-article","created":{"date-parts":[[2004,6,10]],"date-time":"2004-06-10T10:19:45Z","timestamp":1086862785000},"page":"140-147","source":"Crossref","is-referenced-by-count":0,"title":["Hardware assisted two dimensional ultra fast placement"],"prefix":"10.1109","author":[{"given":"M.","family":"Handa","sequence":"first","affiliation":[]},{"given":"R.","family":"Vemuri","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"3","DOI":"10.1109\/54.825678"},{"key":"2","article-title":"Two flows for partial reconfiguration: Module based or small bit manipulations","volume":"290","year":"2002","journal-title":"Xilinx Application Note 290"},{"key":"10","article-title":"Hardware-assisted simulated annealing with application for fast FPGA placement","author":"wrighton","year":"2003","journal-title":"Proceedings of the International Symposium on Field-Programmable Gate Arrays"},{"year":"2001","journal-title":"JBits Reference Manual Release 2 8","key":"1"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.1109\/DATE.2004.1268958"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1109\/FPGA.1998.707919"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1145\/275107.275132"},{"key":"4","doi-asserted-by":"crossref","first-page":"182","DOI":"10.1007\/3-540-44687-7_19","article-title":"Chip-based reconfigurable task management","author":"brebner","year":"2001","journal-title":"Field Programmable Logic and Applications"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1109\/ACAC.2001.903375"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/IPDPS.2003.1213329"},{"year":"0","author":"youssef","journal-title":"VLSI Physical Design Automation Theory and Practice","key":"11"}],"event":{"name":"18th International Parallel and Distributed Processing Symposium, 2004.","location":"Santa Fe, NM, USA"},"container-title":["18th International Parallel and Distributed Processing Symposium, 2004. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9132\/28950\/01303117.pdf?arnumber=1303117","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T03:57:42Z","timestamp":1497585462000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1303117\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/ipdps.2004.1303117","relation":{},"subject":[]}}