{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T23:30:19Z","timestamp":1725492619199},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/ipdps.2004.1303140","type":"proceedings-article","created":{"date-parts":[[2004,6,10]],"date-time":"2004-06-10T14:19:45Z","timestamp":1086877185000},"page":"152-159","source":"Crossref","is-referenced-by-count":0,"title":["MemMap-pd: performance driven technology mapping algorithm for FPGAs with embedded memory arrays"],"prefix":"10.1109","author":[{"given":"A.M.","family":"Kumar","sequence":"first","affiliation":[]},{"given":"B.","family":"Jayaram","sequence":"additional","affiliation":[]},{"given":"R.","family":"Manimegalai","sequence":"additional","affiliation":[]},{"given":"V.","family":"Kamakoti","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1147\/rd.261.0100"},{"key":"16","article-title":"MemMap: Technology mapping algorithm for area minimization in FPGAs with embedded memory blocks using reconvergence analysis","author":"manoj kumar","year":"2003","journal-title":"Technical Report"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/54.156154"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114926"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/43.822620"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275138"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1992.276199"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114928"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1991.185334"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1995.528842"},{"journal-title":"Actel's Reprogrammable SPGAs","year":"1996","key":"7"},{"journal-title":"Datasheet 3200DX Field-programmable Gate Arrays","year":"1995","key":"6"},{"journal-title":"Databook","year":"1996","key":"5"},{"journal-title":"XC4000 Series (E\/L\/EX\/XL) Field Programmable Gate Arrays V1 04","year":"1996","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1995.518232"},{"journal-title":"Datasheet IspLSI and PLSI 6192 High Density Programmable Logic with Dedicated Memory and Register\/Counter Modules","year":"1996","key":"8"}],"event":{"name":"18th International Parallel and Distributed Processing Symposium, 2004.","location":"Santa Fe, NM, USA"},"container-title":["18th International Parallel and Distributed Processing Symposium, 2004. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9132\/28950\/01303140.pdf?arnumber=1303140","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T01:33:44Z","timestamp":1489455224000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1303140\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/ipdps.2004.1303140","relation":{},"subject":[]}}