{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T11:38:06Z","timestamp":1742384286345,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1109\/ipdps.2006.1639271","type":"proceedings-article","created":{"date-parts":[[2006,7,10]],"date-time":"2006-07-10T15:59:56Z","timestamp":1152547196000},"page":"10 pp.","source":"Crossref","is-referenced-by-count":9,"title":["Improving cache locality for thread-level speculation"],"prefix":"10.1109","author":[{"given":"S.L.C.","family":"Fung","sequence":"first","affiliation":[]},{"given":"J.G.","family":"Steffan","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1145\/1082469.1082471"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/113445.113449"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1994.288164"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/277830.277850"},{"key":"11","doi-asserted-by":"crossref","first-page":"48","DOI":"10.1109\/ISCA.1995.524548","article-title":"Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors","author":"lebeck","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379250"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/195473.195557"},{"key":"2","article-title":"Speculative precomputation on chip multiprocessors","volume":"6","author":"brown","year":"2001","journal-title":"Proceedings of MEAC"},{"key":"1","article-title":"Effective hardware-based data prefetching for high-performance processors","volume":"44","author":"baer","year":"1995","journal-title":"IEEE Transactions on Computers"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339669"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/291069.291020"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1998.650559"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1992.697004"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.1993.92"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/12.795218"},{"key":"8","article-title":"Physical experimentation with prefetching helper threads on Intel's hyper-threaded processors","author":"kim","year":"2004","journal-title":"Proc CGO '04"}],"event":{"name":"Proceedings 20th IEEE International Parallel & Distributed Processing Symposium","start":{"date-parts":[[2006,4,25]]},"location":"Rhodes Island, Greece","end":{"date-parts":[[2006,4,29]]}},"container-title":["Proceedings 20th IEEE International Parallel &amp; Distributed Processing Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10917\/34366\/01639271.pdf?arnumber=1639271","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,5,7]],"date-time":"2023-05-07T20:55:01Z","timestamp":1683492901000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1639271\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/ipdps.2006.1639271","relation":{},"subject":[],"published":{"date-parts":[[2006]]}}}