{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,19]],"date-time":"2026-03-19T21:02:23Z","timestamp":1773954143456,"version":"3.50.1"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1109\/ipdps.2006.1639290","type":"proceedings-article","created":{"date-parts":[[2006,7,10]],"date-time":"2006-07-10T19:59:56Z","timestamp":1152561596000},"page":"10 pp.","source":"Crossref","is-referenced-by-count":2,"title":["SAMIE-LSQ: set-associative multiple-instruction entry load\/store queue"],"prefix":"10.1109","author":[{"given":"J.","family":"Abella","sequence":"first","affiliation":[]},{"given":"A.","family":"Gonzalez","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","year":"2000"},{"key":"13","article-title":"CACTI 3.0: An Integrated Cache Timing, Power and Area Model","author":"shivakumar","year":"2001"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765938"},{"key":"11","year":"0"},{"key":"12","doi-asserted-by":"crossref","DOI":"10.1109\/MICRO.2003.1253244","article-title":"Scalable Hardware Memory Disambiguation for High ILP Processors","author":"sethumadhavan","year":"2003","journal-title":"Proc 35th International Symposium on Microarchitecture (MICRO)"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694770"},{"key":"2","doi-asserted-by":"crossref","DOI":"10.1145\/1028176.1006709","article-title":"Memory Ordering: A Value Based Definition","author":"cain","year":"2004","journal-title":"Proceedings of the 31st International Symposium on Computer Architecture (ISCA'04)"},{"key":"1","year":"0"},{"key":"10","year":"0"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871569"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1997.604684"},{"key":"5","article-title":"Two Techniques to Enhance the Performance of Memory Consistency Models","author":"gharachorloo","year":"1991","journal-title":"proceedings of the International Conference on Parallel Processing (ICPP'91)"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/12.509907"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253245"},{"key":"8","article-title":"Dynamic Memory Disambiguation in the Presence of Out-of-order Store Issuing","author":"onder","year":"1999","journal-title":"Proceedings of the 39th International Symposium on Microarchitecture (MICRO)"}],"event":{"name":"Proceedings 20th IEEE International Parallel & Distributed Processing Symposium","location":"Rhodes Island, Greece","start":{"date-parts":[[2006,4,25]]},"end":{"date-parts":[[2006,4,29]]}},"container-title":["Proceedings 20th IEEE International Parallel &amp; Distributed Processing Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10917\/34366\/01639290.pdf?arnumber=1639290","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,17]],"date-time":"2017-06-17T07:22:55Z","timestamp":1497684175000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1639290\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/ipdps.2006.1639290","relation":{},"subject":[],"published":{"date-parts":[[2006]]}}}