{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,26]],"date-time":"2026-09-26T07:18:00Z","timestamp":1790407080277,"version":"4.1.0"},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1109\/ipdps.2006.1639375","type":"proceedings-article","created":{"date-parts":[[2006,7,10]],"date-time":"2006-07-10T19:59:56Z","timestamp":1152561596000},"page":"10 pp.","source":"Crossref","is-referenced-by-count":12,"title":["Helper thread prefetching for loosely-coupled multiprocessor systems"],"prefix":"10.1109","author":[{"family":"Changhee Jung","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Daeseob Lim","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Jaejin Lee","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Y.","family":"Solihin","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379247"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937426"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/12.966498"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003576"},{"key":"15","doi-asserted-by":"crossref","first-page":"269","DOI":"10.1109\/MICRO.2000.898077","article-title":"A study of slipstream processors","author":"purser","year":"2000","journal-title":"Proc 33rd Int'l Symp Microarchitecture (MICRO-33)"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903250"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379250"},{"key":"14","year":"0","journal-title":"Technical Brief NVIDIA nForce Integrated Graphics Processor (IGP) and Dynamic Adaptive Speculative Pre-Processor (DASP)"},{"key":"11","doi-asserted-by":"crossref","first-page":"159","DOI":"10.1145\/605397.605415","article-title":"Design and Evaluation of Compiler Algorithms for Pre-Execution","author":"kim","year":"2002","journal-title":"the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X)"},{"key":"12","article-title":"Automatically mapping code in an intelligent memory architecture","author":"lee","year":"2001","journal-title":"Proc 7th Int l Symp High-Performance Computer Architecture"},{"key":"21","first-page":"172","article-title":"Understanding the backward slices of performance degrading instructions","author":"zilles","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765950"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1145\/335231.335248"},{"key":"2","article-title":"Speculative Precomputation on Chip Multiprocessors","author":"brown","year":"2002","journal-title":"6th Workshop on Multithreaded Execution Architecture (MTEAC-6)"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1996.501191"},{"key":"10","first-page":"27","article-title":"Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processor","author":"kim","year":"2004","journal-title":"the 2nd International Symposium on Code Generation and Optimization (CGO 2004)"},{"key":"7","year":"0"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2002.1105971"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44570-6_3"},{"key":"4","doi-asserted-by":"crossref","DOI":"10.1109\/MICRO.2001.991128","article-title":"Dynamic speculative precomputation","author":"collins","year":"2001","journal-title":"Proceedings of The 34th International Symposium on Microarchitecture (MICRO-34)"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1990.134547"},{"key":"8","year":"0"}],"event":{"name":"Proceedings 20th IEEE International Parallel & Distributed Processing Symposium","location":"Rhodes Island, Greece","start":{"date-parts":[[2006,4,25]]},"end":{"date-parts":[[2006,4,29]]}},"container-title":["Proceedings 20th IEEE International Parallel & Distributed Processing Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10917\/34366\/01639375.pdf?arnumber=1639375","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,7,29]],"date-time":"2021-07-29T13:02:58Z","timestamp":1627563778000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1639375\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/ipdps.2006.1639375","relation":{},"subject":[],"published":{"date-parts":[[2006]]}}}