{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T06:09:48Z","timestamp":1725430188049},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1109\/ipdps.2006.1639431","type":"proceedings-article","created":{"date-parts":[[2006,7,10]],"date-time":"2006-07-10T19:59:56Z","timestamp":1152561596000},"page":"8 pp.","source":"Crossref","is-referenced-by-count":5,"title":["Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor"],"prefix":"10.1109","author":[{"given":"Y.","family":"Hasegawa","sequence":"first","affiliation":[]},{"given":"S.","family":"Abe","sequence":"additional","affiliation":[]},{"given":"S.","family":"Kurotaki","sequence":"additional","affiliation":[]},{"family":"Vu Manh Tuan","sequence":"additional","affiliation":[]},{"given":"N.","family":"Katsura","sequence":"additional","affiliation":[]},{"given":"T.","family":"Nakamura","sequence":"additional","affiliation":[]},{"given":"T.","family":"Nishimura","sequence":"additional","affiliation":[]},{"given":"H.","family":"Amano","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Xilinx","year":"0","key":"13"},{"year":"0","key":"11"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2004.1393261"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1023\/A:1025699015398"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2005.1568541"},{"journal-title":"Elixent","year":"0","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/503048.503072"},{"key":"7","article-title":"A Dynamically Reconfigurable Processor Architecture","author":"motomura","year":"2002","journal-title":"Microprocessor Forum"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/611843.611844"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/IROS.2005.1545033"},{"journal-title":"IPFlex","year":"0","key":"4"},{"key":"9","first-page":"312","article-title":"A Flexible Power Model for FPGAs","author":"poon","year":"2002","journal-title":"Proc Int Conf Field Programmable Logic and Applications"},{"year":"0","key":"8"}],"event":{"name":"Proceedings 20th IEEE International Parallel & Distributed Processing Symposium","start":{"date-parts":[[2006,4,25]]},"location":"Rhodes Island, Greece","end":{"date-parts":[[2006,4,29]]}},"container-title":["Proceedings 20th IEEE International Parallel &amp; Distributed Processing Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10917\/34366\/01639431.pdf?arnumber=1639431","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T15:59:58Z","timestamp":1489507198000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1639431\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/ipdps.2006.1639431","relation":{},"subject":[],"published":{"date-parts":[[2006]]}}}