{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T17:54:41Z","timestamp":1725386081022},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1109\/ipdps.2006.1639438","type":"proceedings-article","created":{"date-parts":[[2006,7,10]],"date-time":"2006-07-10T19:59:56Z","timestamp":1152561596000},"page":"8 pp.","source":"Crossref","is-referenced-by-count":1,"title":["A high-level target-precise model for designing reconfigurable HW tasks"],"prefix":"10.1109","author":[{"given":"M.","family":"Boden","sequence":"first","affiliation":[{"name":"Fraunhofer IIS, Dresden, Germany"}]},{"given":"S.","family":"Rulke","sequence":"additional","affiliation":[{"name":"Fraunhofer IIS, Dresden, Germany"}]},{"given":"J.","family":"Becker","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"year":"0","key":"3"},{"journal-title":"PACT XPP - A Self-Reconfigurable Data Processing Architecture ERSA","year":"2001","author":"baumgarte","key":"2"},{"journal-title":"Online Scheduling for Blockpartitioned Reconfigurable Devices","year":"2003","author":"waldner","key":"10"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2005.242"},{"key":"7","article-title":"Reconfigurable Computing: The Roadmap to a New Business Model - and its Impact on SoC Design","author":"hartenstein","year":"2001","journal-title":"15th SBCCI Brasilia DF"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915091"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/RAWCON.2002.1030109"},{"key":"4","article-title":"ESM: The Erlangen Slot Machine-Architecture and Development Tools","author":"bobda","year":"2005","journal-title":"The Future of Reconfigurable Computing DATE 05 Friday Workshop"},{"journal-title":"RSI research report","article-title":"J. Lesieutre, Z. Wang, On a Generalization of the Collatz Conjecture","year":"2004","key":"9"},{"year":"0","key":"8"},{"article-title":"5V Field Programmable Gate Arrays, Product Specification, DS003-1, Xilinx Inc","year":"2001","author":"virtex","key":"11"}],"event":{"name":"Proceedings. 20th International Parallel and Distributed Processing Symposium","start":{"date-parts":[[2006,4,25]]},"location":"Rhodes, Greece","end":{"date-parts":[[2006,4,29]]}},"container-title":["Proceedings 20th IEEE International Parallel & Distributed Processing Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10917\/34366\/01639438.pdf?arnumber=1639438","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,6,9]],"date-time":"2021-06-09T10:47:01Z","timestamp":1623235621000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/1639438\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/ipdps.2006.1639438","relation":{},"subject":[],"published":{"date-parts":[[2006]]}}}