{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T06:24:22Z","timestamp":1730269462875,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1109\/ipdps.2006.1639490","type":"proceedings-article","created":{"date-parts":[[2006,7,10]],"date-time":"2006-07-10T15:59:56Z","timestamp":1152547196000},"page":"4 pp.","source":"Crossref","is-referenced-by-count":1,"title":["Power consumption advantage of a dynamic optically reconfigurable gate array"],"prefix":"10.1109","author":[{"given":"M.","family":"Watanabe","sequence":"first","affiliation":[]},{"given":"F.","family":"Kobayashi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"13","first-page":"336","article-title":"A 51,272-gate-count Dynamic Optically Reconfigurable Gate Array in a standard 0.35um CMOS Technology","author":"watanabe","year":"2005","journal-title":"International Conference on Solid State Devices and Materials"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2004.1362436"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-30117-2_28"},{"key":"3","first-page":"47","article-title":"Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density","author":"dehon","year":"1996","journal-title":"Fourth Canadian Workshop on Field Programmable Devices"},{"year":"0","key":"2"},{"key":"1","first-page":"99","article-title":"development of dynamically reconfigurable processor lsi","volume":"56","author":"nakano","year":"2003","journal-title":"NEC Tech J (Japan)"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1464812"},{"key":"7","first-page":"763","article-title":"Optically Programmable Gate Array","volume":"4089","author":"mumbru","year":"2000","journal-title":"SPIE of Optics in Computing"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1995.518231"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1997.624601"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707884"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/SSMSD.2000.836438"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1117\/12.363963"}],"event":{"name":"Proceedings 20th IEEE International Parallel & Distributed Processing Symposium","start":{"date-parts":[[2006,4,25]]},"location":"Rhodes Island, Greece","end":{"date-parts":[[2006,4,29]]}},"container-title":["Proceedings 20th IEEE International Parallel &amp; Distributed Processing Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10917\/34366\/01639490.pdf?arnumber=1639490","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T11:45:49Z","timestamp":1489491949000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1639490\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/ipdps.2006.1639490","relation":{},"subject":[],"published":{"date-parts":[[2006]]}}}