{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:52:32Z","timestamp":1759146752822,"version":"3.28.0"},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1109\/ipdps.2006.1639611","type":"proceedings-article","created":{"date-parts":[[2006,7,10]],"date-time":"2006-07-10T19:59:56Z","timestamp":1152561596000},"page":"8 pp.","source":"Crossref","is-referenced-by-count":7,"title":["Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework"],"prefix":"10.1109","author":[{"given":"F.","family":"Mehdipour","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.S.","family":"Zamani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H.R.","family":"Ahmadifar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Sedighi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K.","family":"Murakami","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","first-page":"1413","article-title":"Fast data encipherment algorithm FEAL","author":"shimizu","year":"1987","journal-title":"Transaction of IECE of Japan J70-D (7)"},{"key":"22","doi-asserted-by":"crossref","first-page":"115","DOI":"10.1016\/S0141-9331(02)00102-3","article-title":"Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system","volume":"27","author":"tanougast","year":"2003","journal-title":"Microprocessors and Microsystems"},{"article-title":"M, SIS: A system for sequential circuit analysis","year":"1992","author":"sentovich","key":"17"},{"journal-title":"Fast Place and Route Approaches for FPGAs","year":"1999","author":"tessier","key":"23"},{"journal-title":"Algorithms for VLSI Physical Design Automation","year":"1999","author":"sherwani","key":"18"},{"year":"0","key":"24"},{"key":"15","article-title":"A New Iterative Design Flow for Static Compilation of Reconfigurable Computing Systems","author":"mehdipour","year":"2004","journal-title":"Proc 10th Int Symp on Integr Circuits Devices Syst"},{"journal-title":"Synthesis and Optimization of Digital Circuits","year":"1994","author":"micheli","key":"16"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.1999.761102"},{"key":"14","doi-asserted-by":"crossref","first-page":"952","DOI":"10.1109\/TCAD.2003.814237","article-title":"Temporal logic replication for dynamically reconfigurable FPGA partitioning","volume":"22","author":"mak","year":"2003","journal-title":"IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems"},{"journal-title":"Synthesis Techniques and Optimizations for Reconfigurable Systems","year":"2004","author":"kastner","key":"11"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1996.564815"},{"key":"21","first-page":"37","author":"spillane","year":"1998","journal-title":"Temporal partitioning for partially reconfigurable field programmable gate arrays IPPS\/SPDP"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2001.156216"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707892"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/54.825678"},{"journal-title":"A reconfigurable computing primer","year":"1998","author":"barr","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/12.773795"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/508352.508353"},{"year":"0","key":"6"},{"year":"0","key":"5"},{"year":"0","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707932"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"}],"event":{"name":"Proceedings 20th IEEE International Parallel & Distributed Processing Symposium","start":{"date-parts":[[2006,4,25]]},"location":"Rhodes Island, Greece","end":{"date-parts":[[2006,4,29]]}},"container-title":["Proceedings 20th IEEE International Parallel & Distributed Processing Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10917\/34366\/01639611.pdf?arnumber=1639611","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,17]],"date-time":"2017-06-17T07:23:02Z","timestamp":1497684182000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1639611\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/ipdps.2006.1639611","relation":{},"subject":[],"published":{"date-parts":[[2006]]}}}