{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T09:16:55Z","timestamp":1725441415742},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,4]]},"DOI":"10.1109\/ipdps.2008.4536507","type":"proceedings-article","created":{"date-parts":[[2008,6,6]],"date-time":"2008-06-06T16:44:52Z","timestamp":1212770692000},"page":"1-8","source":"Crossref","is-referenced-by-count":2,"title":["HARPE: A Harvard-based processing element tailored for partial dynamic reconfigurable architectures"],"prefix":"10.1109","author":[{"given":"Alessio","family":"Montone","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vincenzo","family":"Rana","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marco D.","family":"Santambrogio","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Donatella","family":"Sciuto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Politecnico","family":"di Milano","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"0","key":"19"},{"key":"22","first-page":"844","author":"horta","year":"1993","journal-title":"Dynamic hardware plugins in an fpga with partial run-time reconfigurtion"},{"journal-title":"Virtex series configuration architecture user guide Xilinx XAPP151","year":"2003","author":"kelem","key":"17"},{"article-title":"generalized rad module interface specification of the field programmable port extender (fpx)","year":"0","author":"taylor","key":"23"},{"year":"0","key":"18"},{"article-title":"parbit: a tool to transform bitfiles to implement partial reconfiguration of field programmable gate arrays (fpgas)","year":"2001","author":"horta","key":"24"},{"year":"2003","key":"15","article-title":"module based or difference based"},{"journal-title":"Early Access Partial Reconfiguration Guide","year":"2006","key":"16"},{"journal-title":"The CoreConnect bus architecture white paper","year":"2004","key":"13"},{"journal-title":"Development System Reference Guide 8 1i","year":"2006","key":"14"},{"journal-title":"Virtex series configuration architecture user guide","year":"2003","key":"11"},{"key":"12","first-page":"717","article-title":"krasteva, didier joly. virtex ii bitstream manipulation: application to reconfiguration control sytems","author":"de la torre teresa","year":"2006","journal-title":"Proc of 16th IEEE Intl Conference on Field Programmable Logic and Applications"},{"journal-title":"Embedded Development Kit EDK 8 2i","year":"2006","key":"21"},{"year":"0","key":"3"},{"journal-title":"Embedded Development Kit EDK 8 2i Xilinx User Guide v6 0","article-title":"xilinx. microblaze processor reference guide","year":"2006","key":"20"},{"year":"2007","key":"2","article-title":"technical report ug191, xilinx inc"},{"year":"2007","key":"1","article-title":"technical report ug71, xilinx inc"},{"journal-title":"Virtex-II Pro and Virtex-II ProX Virtex-II Pro and Virtex-II Pro X FPGA User Guide","year":"2007","key":"10"},{"journal-title":"Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms ERSA 2007","year":"0","author":"koester","key":"7"},{"key":"6","article-title":"design and implementation of the morphosys reconfigurable computing processor","author":"lu","year":"0","journal-title":"J VLSI Signal Process Syst"},{"key":"5","article-title":"piperench: a reconfigurable architecture and compiler","author":"budiu srihari","year":"0","journal-title":"Computer"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/2.204677"},{"year":"0","key":"9"},{"year":"0","key":"8"}],"event":{"name":"Distributed Processing Symposium (IPDPS)","start":{"date-parts":[[2008,4,14]]},"location":"Miami, FL, USA","end":{"date-parts":[[2008,4,18]]}},"container-title":["2008 IEEE International Symposium on Parallel and Distributed Processing"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4519061\/4536075\/04536507.pdf?arnumber=4536507","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T15:26:19Z","timestamp":1489677979000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4536507\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,4]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/ipdps.2008.4536507","relation":{},"ISSN":["1530-2075"],"issn-type":[{"type":"print","value":"1530-2075"}],"subject":[],"published":{"date-parts":[[2008,4]]}}}