{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,29]],"date-time":"2025-05-29T08:07:15Z","timestamp":1748506035260,"version":"3.28.0"},"reference-count":32,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,4]]},"DOI":"10.1109\/ipdps.2008.4536525","type":"proceedings-article","created":{"date-parts":[[2008,6,6]],"date-time":"2008-06-06T16:44:52Z","timestamp":1212770692000},"page":"1-8","source":"Crossref","is-referenced-by-count":2,"title":["Accelerating matrix decomposition with replications"],"prefix":"10.1109","author":[{"family":"Yi-Gang Tai","sequence":"first","affiliation":[]},{"family":"Chia-Tien Dan Lo","sequence":"additional","affiliation":[]},{"family":"Kleanthis Psarris","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.128"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1137\/1.9781611971217"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/1216919.1216927"},{"journal-title":"IBM CoreConnect bus architecture A 32- 64- 128-bit core on-chip bus structure","year":"0","key":"15"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2007.1001"},{"key":"13","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1137\/S0036144503428693","article-title":"recursive blocked algorithms and hybrid data structures for dense matrix library software","volume":"46","author":"elmroth","year":"2004","journal-title":"SIAM Review"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/1055531.1055534"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.728"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046204"},{"key":"21","doi-asserted-by":"crossref","first-page":"221","DOI":"10.1145\/500001.500054","article-title":"synthesis of pipelined memory access controllers for streamed data applications on fpga-based computing engines","author":"park","year":"2001","journal-title":"International Symposium on System Synthesis (IEEE Cat No 01EX526) ISSS-01"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1145\/375977.375978"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380630"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2005.54"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311240"},{"key":"25","first-page":"1","article-title":"automatically tuned linear algebra software","author":"whaley","year":"1998","journal-title":"Supercomputing '98 Proceedings of the 1998 ACM\/IEEE conference on Supercomputing (CDROM)"},{"journal-title":"OPB SYSACE (System ACE) Interface Controller (v1 00c)","year":"2005","key":"26"},{"journal-title":"MicroBlaze Processor Reference Guide","year":"2007","key":"27"},{"journal-title":"PowerPC Processor Reference Guide","year":"2007","key":"28"},{"journal-title":"Virtex-II Pro \/ Virtex-II Pro X Complete Data Sheet","year":"2007","key":"29"},{"journal-title":"GotoBLAS","year":"0","key":"3"},{"journal-title":"BLAS (Basic Linear Algebra Subprograms)","year":"0","key":"2"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/503048.503082"},{"journal-title":"Application Acceleration with FPGA-Based Reconfigurable Computing","year":"0","key":"1"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2005.31"},{"journal-title":"High fidelity deconvolution of moderately resolved sources","year":"1995","author":"briggs","key":"7"},{"key":"6","first-page":"101","article-title":"automatic mapping of nested loops to fpgas","author":"bondhugula","year":"2007","journal-title":"PPoPP '07 Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311238"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2007.01.011"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2005.31"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1137\/1.9780898719604"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.2000.903396"},{"key":"8","article-title":"parallel tiled qr factorization for multicore architectures","author":"buttari","year":"2007","journal-title":"LAPack Working Notes"}],"event":{"name":"Distributed Processing Symposium (IPDPS)","start":{"date-parts":[[2008,4,14]]},"location":"Miami, FL, USA","end":{"date-parts":[[2008,4,18]]}},"container-title":["2008 IEEE International Symposium on Parallel and Distributed Processing"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4519061\/4536075\/04536525.pdf?arnumber=4536525","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T08:55:19Z","timestamp":1497776119000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4536525\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,4]]},"references-count":32,"URL":"https:\/\/doi.org\/10.1109\/ipdps.2008.4536525","relation":{},"ISSN":["1530-2075"],"issn-type":[{"type":"print","value":"1530-2075"}],"subject":[],"published":{"date-parts":[[2008,4]]}}}