{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,22]],"date-time":"2025-02-22T05:34:43Z","timestamp":1740202483017,"version":"3.37.3"},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010]]},"DOI":"10.1109\/ipdps.2010.5470359","type":"proceedings-article","created":{"date-parts":[[2010,6,2]],"date-time":"2010-06-02T20:25:07Z","timestamp":1275510307000},"page":"1-10","source":"Crossref","is-referenced-by-count":12,"title":["QoS aware BiNoC architecture"],"prefix":"10.1109","author":[{"given":"Shih-Hsin","family":"Lo","sequence":"first","affiliation":[]},{"given":"Ying-Cherng","family":"Lan","sequence":"additional","affiliation":[]},{"given":"Hsin-Hsien","family":"Yeh","sequence":"additional","affiliation":[]},{"given":"Wen-Chung","family":"Tsai","sequence":"additional","affiliation":[]},{"given":"Yu-Hen","family":"Hu","sequence":"additional","affiliation":[]},{"given":"Sao-Jie","family":"Chen","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/DATE.2004.1269001"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/MDT.2005.99"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1016\/j.vlsi.2004.07.009"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/ISVLSI.2006.13"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/ISSOC.2004.1411140"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/ISCAS.2005.1464954"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/DATE.2003.1253633"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1145\/356586.356588"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/71.877831"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"260","DOI":"10.1145\/996566.996638","article-title":"DyAD&#x2014;Smart Routing for Networks-on-Chip","author":"hu","year":"2004","journal-title":"Proceedings of the DAC"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/2.976921"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1145\/378239.379048"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1145\/1132952.1132953"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/TPDS.2005.22"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1016\/S0169-7552(98)00261-X"},{"year":"2004","author":"dally","article-title":"Principles and Practices of Interconnection Networks","key":"ref7"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"105","DOI":"10.1016\/j.sysarc.2003.07.004","article-title":"QNoC: QoS Architecture and Design Process for Network on Chip","volume":"50","author":"bolotin","year":"2004","journal-title":"Elsevier Journal of Systems Architecture"},{"year":"1974","author":"gazis","article-title":"Traffic Science","key":"ref1"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/NOCS.2009.5071476"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/MM.2007.4378787"}],"event":{"name":"2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS)","start":{"date-parts":[[2010,4,19]]},"location":"Atlanta, GA, USA","end":{"date-parts":[[2010,4,23]]}},"container-title":["2010 IEEE International Symposium on Parallel &amp; Distributed Processing (IPDPS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5465899\/5470342\/05470359.pdf?arnumber=5470359","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T15:48:58Z","timestamp":1740152938000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5470359\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/ipdps.2010.5470359","relation":{},"subject":[],"published":{"date-parts":[[2010]]}}}