{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,9]],"date-time":"2026-06-09T15:35:30Z","timestamp":1781019330598,"version":"3.54.1"},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,4]]},"DOI":"10.1109\/ipdps.2010.5470445","type":"proceedings-article","created":{"date-parts":[[2010,6,2]],"date-time":"2010-06-02T16:25:07Z","timestamp":1275495907000},"page":"1-10","source":"Crossref","is-referenced-by-count":10,"title":["High performance comparison-based sorting algorithm on many-core GPUs"],"prefix":"10.1109","author":[{"family":"Xiaochun Ye","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Dongrui Fan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Wei Lin","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Nan Yuan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Paolo","family":"Ienne","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1137\/0218014"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1142473.1142511"},{"key":"ref12","first-page":"97","article-title":"Scan primitives for gpu computing","author":"sengupta","year":"2007","journal-title":"GH '07 Proceedings of the 22nd ACM SIGGRAPH\/EUROGRAPHICS Symposium on Graphics Hardware"},{"key":"ref13","article-title":"Parallel prefix sum (scan) with CUDA","author":"harris","year":"2007","journal-title":"GPU Gems 3"},{"key":"ref14","doi-asserted-by":"crossref","DOI":"10.1016\/j.jpdc.2008.05.012","article-title":"Fast parallel gpu-sorting using a hybrid algorithm","author":"sintorn","year":"2008","journal-title":"Journal of Parallel and Distributed Computing"},{"key":"ref15","first-page":"697","article-title":"Broad-phase collision detection with CUDA","author":"le grand","year":"2007","journal-title":"GPU Gems 3"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1362622.1362684"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2009.5161005"},{"key":"ref18","first-page":"246","article-title":"A practical quicksort algorithm for graphics processors","author":"cederman","year":"2008","journal-title":"Proc 16th Annual European Symposium on Algorithms (ESA 2008)"},{"key":"ref19","year":"2009","journal-title":"Nvidia cuda sdk"},{"key":"ref4","year":"0"},{"key":"ref3","year":"0"},{"key":"ref6","first-page":"41","article-title":"Photon mapping on programmable graphics hardware","author":"purcell","year":"2003","journal-title":"Proc ACM SIGGRAPH\/EUROGRAPHICS conference on Graphics hardware"},{"key":"ref5","article-title":"NVIDIA CUDA Programming Guide","year":"2008","journal-title":"Version 2 0"},{"key":"ref8","first-page":"733","article-title":"Improved GPU sorting","author":"kipfer","year":"2005","journal-title":"GPUGems 2 Programming Techniques for High-Performance Graphics and General-Purpose Computation"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360145"},{"key":"ref2","first-page":"21","article-title":"A Survey of General-Purpose Computation on Graphics Hardware","author":"owens","year":"2005","journal-title":"Eurographics 2005 State of the Art Reports"},{"key":"ref1","first-page":"307","article-title":"Sorting networks and their applications","volume":"32","author":"batcher","year":"0","journal-title":"AFIPS Spring Joint Computer Conference"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2006.1639284"},{"key":"ref20","article-title":"Sorting using Bitonic Network with CUDA","author":"baraglia","year":"2009","journal-title":"In the 7th Workshop on Large-Scale Distributed Systems for Information Retrieval (LSDS-IR)"},{"key":"ref22","article-title":"Efficient parallel scan algorithms for GPUs","author":"sengupta","year":"2008","journal-title":"NVIDIA Technical Report NVR-2008-003"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.31"},{"key":"ref24","article-title":"Designing efficient sorting algorithms for manycore GPUs","author":"satish","year":"2008","journal-title":"NVIDIA Technical Report NVR-2008-001"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.57"}],"event":{"name":"Distributed Processing (IPDPS)","location":"Atlanta, GA","start":{"date-parts":[[2010,4,19]]},"end":{"date-parts":[[2010,4,23]]}},"container-title":["2010 IEEE International Symposium on Parallel &amp; Distributed Processing (IPDPS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5465899\/5470342\/05470445.pdf?arnumber=5470445","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T04:58:34Z","timestamp":1497848314000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5470445\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,4]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/ipdps.2010.5470445","relation":{},"subject":[],"published":{"date-parts":[[2010,4]]}}}