{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T01:10:09Z","timestamp":1773796209273,"version":"3.50.1"},"reference-count":36,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010]]},"DOI":"10.1109\/ipdps.2010.5470459","type":"proceedings-article","created":{"date-parts":[[2010,6,2]],"date-time":"2010-06-02T20:25:07Z","timestamp":1275510307000},"page":"1-12","source":"Crossref","is-referenced-by-count":24,"title":["DynTile: Parametric tiled loop generation for parallel execution on multicore processors"],"prefix":"10.1109","author":[{"given":"Albert","family":"Hartono","sequence":"first","affiliation":[]},{"given":"Muthu Manikandan","family":"Baskaran","sequence":"additional","affiliation":[]},{"given":"J.","family":"Ramanujam","sequence":"additional","affiliation":[]},{"given":"P.","family":"Sadayappan","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","article-title":"Scalable autotuning framework for compiler optimization","author":"tiwari","year":"2009","journal-title":"IPDPS '09"},{"key":"ref32","article-title":"Automatic blocking of nested loops","author":"schreiber","year":"1990","journal-title":"Tech Report 90 38 RIACS NASA Ames Research Center"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1250734.1250780"},{"key":"ref30","first-page":"108","article-title":"Tiling multidimensional iteration spaces for multicomputers","volume":"16","author":"ramanujam","year":"1992","journal-title":"JPDC"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-4337-4"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/SC.1998.10004"},{"key":"ref34","year":"0","journal-title":"TLoG A Parametrized Tiled Loop Generator"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/0167-9260(94)90019-1"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2005.10"},{"key":"ref12","article-title":"A framework for composing high-level loop transformations","author":"chen","year":"2008","journal-title":"Technical Report 08–897 USC Computer Science Technical Report"},{"key":"ref13","article-title":"CLooG: The Chunky Loop Generator","year":"0"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/BF01407931"},{"key":"ref15","article-title":"Automatic Parallelization of Loop Programs for Distributed Memory Architectures","author":"griebl","year":"2004","journal-title":"FMI University of Passau"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1542275.1542301"},{"key":"ref17","year":"0","journal-title":"HiTLoG Hierarchical Tiled Loop Generator"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/305619.305641"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/73560.73588"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/135226.135233"},{"key":"ref4","article-title":"Workshop on Automatic Tuning for Petascale Systems","year":"0"},{"key":"ref27","year":"0","journal-title":"PrimeTile A Parametric Multi-Level Tiler for Imperfect Loop Nests"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/109625.109631"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISPDC.2003.1267639"},{"key":"ref29","first-page":"469","article-title":"Generation of efficient nested loops from polyhedra","volume":"28","author":"quillere","year":"2000","journal-title":"IJPP"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1772954.1772983"},{"key":"ref8","article-title":"Extracting polyhedral representation from high level languages","author":"bastoul","year":"2008","journal-title":"Universite Paris Sud' Tech Rep"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2004.1342537"},{"key":"ref2","article-title":"Synthesizing transformations for locality enhancement of imperfectly-nested loop nests","volume":"29","author":"ahmed","year":"2001","journal-title":"IJPP"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1375581.1375595"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2000.10018"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/567097.567101"},{"key":"ref22","article-title":"Parameterized tiling for imperfectly nested loops","author":"kim","year":"2009","journal-title":"Technical Report CS-09–101 Colorado State University Department of Computer Science"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2003.1239869"},{"key":"ref24","article-title":"Improving Parallelism And Data Locality With Affine Partitioning","author":"lim","year":"2001"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1362622.1362691"},{"key":"ref26","year":"0","journal-title":"Pluto A Polyhedral Automatic Parallelizer and Locality Optimizer for Multicores"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-8191(98)00021-0"}],"event":{"name":"2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS)","location":"Atlanta, GA, USA","start":{"date-parts":[[2010,4,19]]},"end":{"date-parts":[[2010,4,23]]}},"container-title":["2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5465899\/5470342\/05470459.pdf?arnumber=5470459","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,19]],"date-time":"2017-03-19T05:15:25Z","timestamp":1489900525000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5470459\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010]]},"references-count":36,"URL":"https:\/\/doi.org\/10.1109\/ipdps.2010.5470459","relation":{},"subject":[],"published":{"date-parts":[[2010]]}}}