{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T06:24:16Z","timestamp":1730269456016,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,4]]},"DOI":"10.1109\/ipdpsw.2010.5470778","type":"proceedings-article","created":{"date-parts":[[2010,5,28]],"date-time":"2010-05-28T14:25:42Z","timestamp":1275056742000},"page":"1-7","source":"Crossref","is-referenced-by-count":1,"title":["Performance impact of SMP-cluster on the On-chip Large-scale Parallel Computing architecture"],"prefix":"10.1109","author":[{"given":"Shenggang","family":"Chen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shuming","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Yaming Yin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"1569","article-title":"How does communication influence cluster's parallel computing performance","volume":"24","author":"hu","year":"2003","journal-title":"Mini-Micro Systems"},{"journal-title":"Principles and Practices of Interconnection Networks","year":"2004","author":"dally","key":"ref11"},{"key":"ref12","first-page":"105","article-title":"Speedup analysis of data-parallel applications on multi-core nocs","author":"chen","year":"2009","journal-title":"Proc of IEEE 8th international Conference on ASIC"},{"journal-title":"Computer Architecture A Quantitative Approach","year":"2007","author":"hennessy","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.11"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/384265.291020"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346182"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378781"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2008.209"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250686"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798252"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.3724\/SP.J.1016.2008.01948"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391666"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.239"},{"journal-title":"Tiled multicore processors The four stages of reality","year":"2008","author":"agarwal","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CCGRID.2007.119"}],"event":{"name":"Distributed Processing, Workshops and Phd Forum (IPDPSW)","start":{"date-parts":[[2010,4,19]]},"location":"Atlanta, GA, USA","end":{"date-parts":[[2010,4,23]]}},"container-title":["2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5465895\/5470678\/05470778.pdf?arnumber=5470778","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,19]],"date-time":"2017-03-19T01:50:54Z","timestamp":1489888254000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5470778\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,4]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/ipdpsw.2010.5470778","relation":{},"subject":[],"published":{"date-parts":[[2010,4]]}}}