{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,22]],"date-time":"2025-02-22T05:26:19Z","timestamp":1740201979831,"version":"3.37.3"},"reference-count":35,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,4]]},"DOI":"10.1109\/ipdpsw.2010.5470906","type":"proceedings-article","created":{"date-parts":[[2010,5,28]],"date-time":"2010-05-28T18:25:42Z","timestamp":1275071142000},"page":"1-8","source":"Crossref","is-referenced-by-count":1,"title":["Integrated energy-aware cyclic and acyclic scheduling for clustered VLIW processors"],"prefix":"10.1109","author":[{"given":"Jimmy","family":"Bahuleyan","sequence":"first","affiliation":[]},{"given":"Rahul","family":"Nagpal","sequence":"additional","affiliation":[]},{"given":"Y. N.","family":"Srikant","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"year":"0","key":"ref33"},{"journal-title":"The Trimaran Compiler Infrastructure","year":"0","key":"ref32"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/581630.581663"},{"key":"ref30","first-page":"295","article-title":"Exploiting software pipelining for network-on-chip architectures","author":"li","year":"2006","journal-title":"ISVLSI"},{"key":"ref35","first-page":"39","article-title":"Netbench: A bench-marking suite for network processors","author":"memik","year":"2001","journal-title":"ICCAD"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/WWC.2001.990739"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176243"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742773"},{"key":"ref12","first-page":"308","article-title":"Unified assign and schedule: a new approach to scheduling for clustered register file microarchitectures","author":"\u00f6zer","year":"1998","journal-title":"Micro 31"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2000.888353"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903258"},{"key":"ref15","first-page":"160","article-title":"Modulo scheduling with integrated register spilling for clustered vliw architectures","author":"zalamea","year":"2001","journal-title":"MICRO-34"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"457","DOI":"10.1145\/977091.977155","article-title":"Integrated temporal and spatial scheduling for extended operand clustered vliw processors","author":"nagpal","year":"2004","journal-title":"CF"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1002\/spe.826"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/C-M.1981.220595"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1014192.802449"},{"key":"ref28","first-page":"40","article-title":"Power-aware modulo scheduling for highperformance vliw processors","author":"yun","year":"2001","journal-title":"ISPLED"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176260"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1176887.1176921"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360148"},{"article-title":"Bulldog: a compiler for VLIWarchitectures","year":"1986","author":"ellis","key":"ref6"},{"key":"ref29","first-page":"111","article-title":"Distributed Embedded Systems: Design, Middleware and Resources","author":"wang","year":"2008","journal-title":"ser IFIP"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/780822.781165"},{"key":"ref8","first-page":"150","article-title":"Graph-partitioning based instruction scheduling for clustered processors","author":"alet\u00e0","year":"2001","journal-title":"MICRO-34"},{"key":"ref7","article-title":"Instruction assignment for clustered vliw dsp compilers: A new approach","author":"desoli","year":"1998","journal-title":"Technical report of Hewlett Packard"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/780732.780770"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/567270.567274"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/2.917539"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/BF01759032"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2001.991109"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192731"},{"key":"ref24","first-page":"227","article-title":"Energy-optimal integrated vliw code gen-eration","author":"bednarski","year":"2004","journal-title":"Proc Workshop Compilers for Parallel Computers"},{"key":"ref23","first-page":"261","article-title":"Optimizing static power dissipation by functional units in superscalar processors","author":"rele","year":"0","journal-title":"CCC 2002"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1275937.1275942"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1023\/B:VLSI.0000017007.28247.f6"}],"event":{"name":"Distributed Processing, Workshops and Phd Forum (IPDPSW)","start":{"date-parts":[[2010,4,19]]},"location":"Atlanta, GA, USA","end":{"date-parts":[[2010,4,23]]}},"container-title":["2010 IEEE International Symposium on Parallel &amp; Distributed Processing, Workshops and Phd Forum (IPDPSW)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5465895\/5470678\/05470906.pdf?arnumber=5470906","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:32:22Z","timestamp":1740133942000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5470906\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,4]]},"references-count":35,"URL":"https:\/\/doi.org\/10.1109\/ipdpsw.2010.5470906","relation":{},"subject":[],"published":{"date-parts":[[2010,4]]}}}