{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T12:02:44Z","timestamp":1725710564088},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,4]]},"DOI":"10.1109\/irps.2015.7112673","type":"proceedings-article","created":{"date-parts":[[2015,6,3]],"date-time":"2015-06-03T19:32:57Z","timestamp":1433359977000},"page":"2B.2.1-2B.2.6","source":"Crossref","is-referenced-by-count":1,"title":["Power debug on Fully Integrated Voltage Regulators (FIVR) circuitry introduced deep low power states"],"prefix":"10.1109","author":[{"given":"Yuan-Chuan Steven","family":"Chen","sequence":"first","affiliation":[]},{"given":"Dave","family":"Budka","sequence":"additional","affiliation":[]},{"given":"Auston","family":"Gibertini","sequence":"additional","affiliation":[]},{"given":"Joe","family":"Davis","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","article-title":"Design Validation on Multiple-Core CPU Supported Low Power States Using Platform Based Infrared Emission Microscopy (PIREM) Technique","author":"steven chen","year":"0","journal-title":"2012 VLSI-TSA"},{"key":"ref3","article-title":"FIVR-Fully Integrated Voltage Regulators on 4th Generation Intel® Core™ SoCs","author":"burton","year":"0","journal-title":"IEEE 2014 Applied Power Electronics Conference and Exposition (APEC)"},{"journal-title":"Datasheet of Mobile 3rd Generation Intel® Core™ Processor Family Mobile Intel® Pentium® Processor Family and Mobile Intel® Celeron® Processor Family","year":"0","key":"ref6"},{"key":"ref5","article-title":"Infrared Emission-Based Static Logic State Imaging on Advanced Silicon Technologies","author":"bockelman","year":"2002","journal-title":"IEEE IST"},{"key":"ref7","article-title":"Self-healt Reliability Considerations on Intel's 22nm Tri-gate Technology","author":"prasad","year":"2013","journal-title":"IEEE IRPS"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757361"},{"key":"ref1","article-title":"A 22 nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gat Transistors, Self-Aligned Contacts and High Density MIM Capacitors","author":"auth","year":"2012","journal-title":"IEEE VLSI"}],"event":{"name":"2015 IEEE International Reliability Physics Symposium (IRPS)","start":{"date-parts":[[2015,4,19]]},"location":"Monterey, CA, USA","end":{"date-parts":[[2015,4,23]]}},"container-title":["2015 IEEE International Reliability Physics Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7106273\/7112653\/07112673.pdf?arnumber=7112673","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T21:04:21Z","timestamp":1490389461000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7112673\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,4]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/irps.2015.7112673","relation":{},"subject":[],"published":{"date-parts":[[2015,4]]}}}