{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,17]],"date-time":"2026-01-17T21:36:32Z","timestamp":1768685792793,"version":"3.49.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,4]]},"DOI":"10.1109\/irps.2015.7112712","type":"proceedings-article","created":{"date-parts":[[2015,6,3]],"date-time":"2015-06-03T19:32:57Z","timestamp":1433359977000},"page":"3D.2.1-3D.2.6","source":"Crossref","is-referenced-by-count":14,"title":["Localized thermal effect of sub-16nm FinFET technologies and its impact on circuit reliability designs and methodologies"],"prefix":"10.1109","author":[{"given":"Yongsheng","family":"Sun","sequence":"first","affiliation":[]},{"given":"Canhui","family":"Zhan","sequence":"additional","affiliation":[]},{"given":"Jianping","family":"Guo","sequence":"additional","affiliation":[]},{"given":"Yiwei","family":"Fu","sequence":"additional","affiliation":[]},{"given":"Guangming","family":"Li","sequence":"additional","affiliation":[]},{"given":"Jun","family":"Xia","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ITHERM.2006.1645410"},{"key":"ref3","first-page":"71","article-title":"Simulation of self-heating effects in 30nmgate length FinFET","author":"braccioli","year":"2008","journal-title":"Proc ULIS"},{"key":"ref10","first-page":"7.6.1","article-title":"Reliability study of CMOS FinFETs","author":"choi","year":"2003","journal-title":"IEEE IEDM"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2013.6532036"},{"key":"ref11","article-title":"Monolithic phase-locked loops and clock recovery circuits: theory and design","author":"bazavi","year":"1996"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000455"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418895"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2014.6860642"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2006.870340"},{"key":"ref9","first-page":"4c.5.1","article-title":"Intrinsic transistor reliability improvements from 22nm tri-gate technology","author":"ramey","year":"2013","journal-title":"Proc IRPS"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2248194"}],"event":{"name":"2015 IEEE International Reliability Physics Symposium (IRPS)","location":"Monterey, CA, USA","start":{"date-parts":[[2015,4,19]]},"end":{"date-parts":[[2015,4,23]]}},"container-title":["2015 IEEE International Reliability Physics Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7106273\/7112653\/07112712.pdf?arnumber=7112712","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T19:20:29Z","timestamp":1490383229000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7112712\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,4]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/irps.2015.7112712","relation":{},"subject":[],"published":{"date-parts":[[2015,4]]}}}