{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T09:44:02Z","timestamp":1725443042044},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,4]]},"DOI":"10.1109\/irps.2015.7112797","type":"proceedings-article","created":{"date-parts":[[2015,6,3]],"date-time":"2015-06-03T19:32:57Z","timestamp":1433359977000},"page":"EL.6.1-EL.6.5","source":"Crossref","is-referenced-by-count":0,"title":["Enhanced CDM-robustness for the packaged IC with the extra bonding wire to the die-attach plate"],"prefix":"10.1109","author":[{"given":"Tzu-Cheng","family":"Kao","sequence":"first","affiliation":[]},{"given":"Jian-Hsing","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Chen-Hsin","family":"Lien","sequence":"additional","affiliation":[]},{"given":"Chih-Hsien","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Kuang-Cheng","family":"Tai","sequence":"additional","affiliation":[]},{"given":"Hung-Der","family":"Su","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2010.5488782"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/S0026-2714(03)00276-2"},{"key":"ref10","first-page":"228","article-title":"The study of sensitive circuit and layout for CDM improvement","author":"lee","year":"2009","journal-title":"Proc Int Symp Phys Failure Anal Integr Circ"},{"key":"ref6","first-page":"421","article-title":"Investigation on CDM ESD events on core circuits in 65-nm CMOS process","author":"lin","year":"2003","journal-title":"Microelectronics Reliability"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/EOSESD.2004.5272622"},{"journal-title":"JEDEC","article-title":"JESD22-C101-E: Field-Induced Charged Device Model Test Method for Electrostatic Discharge-Withstand thresholds of Microelectronic Components","year":"2009","key":"ref8"},{"key":"ref7","article-title":"SOI lateral optimization for ESD protection in 130nm and 90nm technologies","author":"salman","year":"2005","journal-title":"Proc EOS\/ESD Symposium"},{"key":"ref2","first-page":"67","article-title":"Chip level charged-device modeling and simulation in CMOS integrated circuits","author":"lee","year":"2003","journal-title":"IEEE Trans Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1983.21093"},{"key":"ref1","first-page":"608","article-title":"Significance of including substrate capacitance in the full chip circuit model of ICs under CDM stress","author":"sworariraj","year":"2005","journal-title":"Proc International Reliability Physics Symp"}],"event":{"name":"2015 IEEE International Reliability Physics Symposium (IRPS)","start":{"date-parts":[[2015,4,19]]},"location":"Monterey, CA, USA","end":{"date-parts":[[2015,4,23]]}},"container-title":["2015 IEEE International Reliability Physics Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7106273\/7112653\/07112797.pdf?arnumber=7112797","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T19:00:12Z","timestamp":1490382012000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7112797\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,4]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/irps.2015.7112797","relation":{},"subject":[],"published":{"date-parts":[[2015,4]]}}}