{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T06:52:39Z","timestamp":1730271159691,"version":"3.28.0"},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,4]]},"DOI":"10.1109\/irps.2015.7112815","type":"proceedings-article","created":{"date-parts":[[2015,6,3]],"date-time":"2015-06-03T19:32:57Z","timestamp":1433359977000},"page":"MY.13.1-MY.13.5","source":"Crossref","is-referenced-by-count":2,"title":["SRAM stability design comprehending 14nm FinFET reliability"],"prefix":"10.1109","author":[{"given":"Choelhwyi","family":"Bae","sequence":"first","affiliation":[]},{"given":"Sangwoo","family":"Pae","sequence":"additional","affiliation":[]},{"given":"Cheong-sik","family":"Yu","sequence":"additional","affiliation":[]},{"given":"Kangjung","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Yongshik","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Jongwoo","family":"Park","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2008.2002351"},{"key":"ref3","first-page":"1023","article-title":"Mature process ability and manufacturability by characterizing VT and VMIN behaviors induced by NBTI and AHTOL test","author":"park","year":"2009","journal-title":"IEEE IRPS"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346778"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2007.910437"},{"key":"ref8","first-page":"138","article-title":"Mechanism of electron trapping and characteristics of traps in HfO2 gate stacks","volume":"7","author":"bersuker","year":"2007","journal-title":"IEEE TDMR"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2013.6531959"},{"key":"ref2","article-title":"CMOS Logic - Technology challenges for the transition from 32 to 22nm, embedded memory: SRAM","author":"kim","year":"2008","journal-title":"VLSI short course"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2008.4558911"},{"key":"ref1","first-page":"105","article-title":"Effects of BTI during AHTOL on SRAM VMIN","author":"lim","year":"2011","journal-title":"IEEE IRPS"}],"event":{"name":"2015 IEEE International Reliability Physics Symposium (IRPS)","start":{"date-parts":[[2015,4,19]]},"location":"Monterey, CA, USA","end":{"date-parts":[[2015,4,23]]}},"container-title":["2015 IEEE International Reliability Physics Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7106273\/7112653\/07112815.pdf?arnumber=7112815","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T19:29:15Z","timestamp":1490383755000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7112815\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,4]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/irps.2015.7112815","relation":{},"subject":[],"published":{"date-parts":[[2015,4]]}}}