{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,12]],"date-time":"2024-09-12T05:07:58Z","timestamp":1726117678640},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.1109\/irps.2018.8353680","type":"proceedings-article","created":{"date-parts":[[2018,5,8]],"date-time":"2018-05-08T21:16:55Z","timestamp":1525814215000},"page":"P-MY.7-1-P-MY.7-4","source":"Crossref","is-referenced-by-count":2,"title":["Error elimination ECC by horizontal error detection and vertical-LDPC ECC to increase data-retention time by 230% and acceptable bit-error rate by 90% for 3D-NAND flash SSDs"],"prefix":"10.1109","author":[{"given":"Shun","family":"Suzuki","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yoshiaki","family":"Deguchi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Toshiki","family":"Nakamura","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kyoji","family":"Mizoguchi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ken","family":"Takeuchi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2280078"},{"key":"ref3","first-page":"112t","article-title":"Reliability Enhancement of 1Xnm TLC for Cold Flash and Millennium Memories","author":"yamazaki","year":"2015","journal-title":"VLSI Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2016.7495285"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2017.7939077"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2014.6849375"},{"key":"ref7","first-page":"136","article-title":"Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices","author":"katsumata","year":"2009","journal-title":"VLSI Tech Dig Tech Papers"},{"key":"ref2","first-page":"204","article-title":"Highly Reliable and Low Power SSD Using Asymmetric Coding and Stripe Bitline-Pattem Elimination Programming","author":"tanakamaru","year":"2011","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref9","first-page":"28","article-title":"AEP-LDPC ECC with Error Dispersion Coding for Burst Error Reduction of2D and 3D NAND Flash Memories","author":"nakamura","year":"2017","journal-title":"Proc IMW"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2380640"}],"event":{"name":"2018 IEEE International Reliability Physics Symposium (IRPS)","start":{"date-parts":[[2018,3,11]]},"location":"Burlingame, CA","end":{"date-parts":[[2018,3,15]]}},"container-title":["2018 IEEE International Reliability Physics Symposium (IRPS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8345372\/8353529\/08353680.pdf?arnumber=8353680","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,6,1]],"date-time":"2018-06-01T18:55:54Z","timestamp":1527879354000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8353680\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/irps.2018.8353680","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}