{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T02:54:11Z","timestamp":1725591251810},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.1109\/irps.2019.8720500","type":"proceedings-article","created":{"date-parts":[[2019,5,24]],"date-time":"2019-05-24T04:11:10Z","timestamp":1558671070000},"page":"1-5","source":"Crossref","is-referenced-by-count":1,"title":["Product Reliability Methods to Enable High Performance CPU's"],"prefix":"10.1109","author":[{"given":"Roman","family":"Rechter","sequence":"first","affiliation":[]},{"given":"Robert","family":"Kwasnick","sequence":"additional","affiliation":[]},{"given":"Almog","family":"Reshef","sequence":"additional","affiliation":[]},{"given":"Oren","family":"Zonensain","sequence":"additional","affiliation":[]},{"given":"Tal","family":"Raz","sequence":"additional","affiliation":[]},{"given":"Anisur","family":"Rahman","sequence":"additional","affiliation":[]},{"given":"Praveen","family":"Polasam","sequence":"additional","affiliation":[]},{"given":"Maxim","family":"Levit","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2011.5784531"},{"journal-title":"Using Big Data In Manufacturing At Intels Smart Factories","year":"2016","author":"chadwick","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-6348-2"},{"year":"0","key":"ref13"},{"journal-title":"Knowledge-based qualification is described in JEP148A JEP122F and JESD94A","year":"0","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/PICMET.2007.4349528"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2007.4425784"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2011.5784455"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2015.25"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2017.7936346"},{"journal-title":"Maximum turbo frequency per CPU generation is described in Intel®Core™ Processors","year":"0","key":"ref2"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9781139195065"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2014.6861172"}],"event":{"name":"2019 IEEE International Reliability Physics Symposium (IRPS)","start":{"date-parts":[[2019,3,31]]},"location":"Monterey, CA, USA","end":{"date-parts":[[2019,4,4]]}},"container-title":["2019 IEEE International Reliability Physics Symposium (IRPS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8712125\/8720395\/08720500.pdf?arnumber=8720500","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,15]],"date-time":"2022-07-15T03:22:17Z","timestamp":1657855337000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8720500\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/irps.2019.8720500","relation":{},"subject":[],"published":{"date-parts":[[2019,3]]}}}