{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T08:06:18Z","timestamp":1725609978410},"reference-count":7,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,4]]},"DOI":"10.1109\/irps45951.2020.9128336","type":"proceedings-article","created":{"date-parts":[[2020,6,30]],"date-time":"2020-06-30T17:20:26Z","timestamp":1593537626000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["Triggering Optimization on NAND ESD Clamp and Its ESD Protection IO Scheme for CMOS Designs"],"prefix":"10.1109","author":[{"given":"Jian","family":"Liu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Divya","family":"Acharya","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nathaniel","family":"Peachey","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2019.8720605"},{"key":"ref3","article-title":"Electrostatic discharge (ESD) protection circuit","author":"peachey","year":"2018","journal-title":"US Patent No"},{"key":"ref6","first-page":"1","article-title":"TLP characterization for testing system level ESD performance","author":"jahanzeb","year":"2010","journal-title":"Electrical Overstress\/Electrostatic Discharge Symposium Proceedings 2010"},{"key":"ref5","first-page":"49","article-title":"Transmission Line Pulsing Techniques for Circuit Modeling of ESD Phenomena","author":"maloney","year":"1985","journal-title":"Proc 8th EOS\/ESD Symposium ESD Association"},{"journal-title":"EOS\/ESD Association Inc","article-title":"ESD Association Technical Report for Electrostatic Discharge Sensitivity Testing – Transmission Line Pulse (TLP) – User and Application Guide","year":"2018","key":"ref7"},{"key":"ref2","article-title":"Unlatch feature for latching ESD protection circuit","author":"peachey","year":"2011","journal-title":"US Patent No"},{"key":"ref1","first-page":"17","article-title":"Boosted and distributed rail clamp networks for ESD protection in advanced CMOS technologies","author":"stockinger","year":"2003","journal-title":"Proc EOS\/ESD Symp"}],"event":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","start":{"date-parts":[[2020,4,28]]},"location":"Dallas, TX, USA","end":{"date-parts":[[2020,5,30]]}},"container-title":["2020 IEEE International Reliability Physics Symposium (IRPS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9125439\/9128217\/09128336.pdf?arnumber=9128336","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,28]],"date-time":"2022-06-28T17:57:10Z","timestamp":1656439030000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9128336\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,4]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/irps45951.2020.9128336","relation":{},"subject":[],"published":{"date-parts":[[2020,4]]}}}