{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,12]],"date-time":"2025-08-12T21:26:50Z","timestamp":1755034010528},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,4]]},"DOI":"10.1109\/irps45951.2020.9128345","type":"proceedings-article","created":{"date-parts":[[2020,6,30]],"date-time":"2020-06-30T21:20:26Z","timestamp":1593552026000},"page":"1-6","source":"Crossref","is-referenced-by-count":11,"title":["A Reliability Overview of Intel\u2019s 10+ Logic Technology"],"prefix":"10.1109","author":[{"given":"R.","family":"Grover","sequence":"first","affiliation":[]},{"given":"T.","family":"Acosta","sequence":"additional","affiliation":[]},{"given":"C.","family":"AnDyke","sequence":"additional","affiliation":[]},{"given":"E.","family":"Armagan","sequence":"additional","affiliation":[]},{"given":"C.","family":"Auth","sequence":"additional","affiliation":[]},{"given":"S.","family":"Chugh","sequence":"additional","affiliation":[]},{"given":"K.","family":"Downes","sequence":"additional","affiliation":[]},{"given":"M.","family":"Hattendorf","sequence":"additional","affiliation":[]},{"given":"N.","family":"Jack","sequence":"additional","affiliation":[]},{"given":"S.","family":"Joshi","sequence":"additional","affiliation":[]},{"given":"R.","family":"Kasim","sequence":"additional","affiliation":[]},{"given":"G.","family":"Leatherman","sequence":"additional","affiliation":[]},{"given":"S.-H.","family":"Lee","sequence":"additional","affiliation":[]},{"given":"C.-Y.","family":"Lin","sequence":"additional","affiliation":[]},{"given":"A.","family":"Madhavan","sequence":"additional","affiliation":[]},{"given":"H.","family":"Mao","sequence":"additional","affiliation":[]},{"given":"A.","family":"Lowrie","sequence":"additional","affiliation":[]},{"given":"G.","family":"Martin","sequence":"additional","affiliation":[]},{"given":"G.","family":"McPherson","sequence":"additional","affiliation":[]},{"given":"P.","family":"Nayak","sequence":"additional","affiliation":[]},{"given":"A.","family":"Neale","sequence":"additional","affiliation":[]},{"given":"D.","family":"Nminibapiel","sequence":"additional","affiliation":[]},{"given":"B.","family":"Orr","sequence":"additional","affiliation":[]},{"given":"J.","family":"Palmer","sequence":"additional","affiliation":[]},{"given":"C.","family":"Pelto","sequence":"additional","affiliation":[]},{"given":"S. S.","family":"Poon","sequence":"additional","affiliation":[]},{"given":"I.","family":"Post","sequence":"additional","affiliation":[]},{"given":"T.","family":"Pramanik","sequence":"additional","affiliation":[]},{"given":"A.","family":"Rahman","sequence":"additional","affiliation":[]},{"given":"S.","family":"Ramey","sequence":"additional","affiliation":[]},{"given":"N.","family":"Seifert","sequence":"additional","affiliation":[]},{"given":"K.","family":"Sethi","sequence":"additional","affiliation":[]},{"given":"A.","family":"Schmitz","sequence":"additional","affiliation":[]},{"given":"H.","family":"Wu","sequence":"additional","affiliation":[]},{"given":"A.","family":"Yeoh","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS45951.2020.9128312"},{"key":"ref11","article-title":"Soft error scaling in 3D tri-gate transistor technologies","author":"seifert","year":"2018","journal-title":"NSREC"},{"key":"ref12","article-title":"Transistor reliability characterization and comparisons for a 14nm tri-gate technology optimized for system-on-chip and foundry platforms","author":"prasad","year":"2016","journal-title":"IRPS"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2009.5173277"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242496"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2018.8353641"},{"key":"ref6","article-title":"A 45nm logic technology with highk+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pbfree packaging","author":"mistry","year":"2007","journal-title":"IEDM"},{"key":"ref5","article-title":"A 14nm logic technology featuring 2nd generation finFET transistors, air-gapped interconnects, self-aligned double patterning, and a 0.0588 um2 SRAM cell size","author":"natarajan","year":"2014","journal-title":"IEDM"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2018.8430489"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2009.5090400"},{"key":"ref2","article-title":"Reliability studies of a 10nm highperformance and low-power CMOS technology featuring 3rd generation finFET and 5th generation HK\/MG","author":"rahman","year":"2018","journal-title":"IRPS"},{"key":"ref1","article-title":"A 10nm high performance and low-power CMOS technology featuring 3rd generation finFET transistors, self-aligned quad patterning, contact over active gate and cobalt local interconnects","author":"auth","year":"2017","journal-title":"IEDM"},{"key":"ref9","article-title":"Low-k interconnect stack with metalinsulator-metal capacitors for 22nm high volume manufacturing","author":"ingerly","year":"2012","journal-title":"IITC"}],"event":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","start":{"date-parts":[[2020,4,28]]},"location":"Dallas, TX, USA","end":{"date-parts":[[2020,5,30]]}},"container-title":["2020 IEEE International Reliability Physics Symposium (IRPS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9125439\/9128217\/09128345.pdf?arnumber=9128345","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,9]],"date-time":"2022-07-09T02:19:37Z","timestamp":1657333177000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9128345\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,4]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/irps45951.2020.9128345","relation":{},"subject":[],"published":{"date-parts":[[2020,4]]}}}