{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,10]],"date-time":"2026-04-10T16:35:51Z","timestamp":1775838951565,"version":"3.50.1"},"reference-count":19,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,3,1]],"date-time":"2023-03-01T00:00:00Z","timestamp":1677628800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,3,1]],"date-time":"2023-03-01T00:00:00Z","timestamp":1677628800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,3]]},"DOI":"10.1109\/irps48203.2023.10118270","type":"proceedings-article","created":{"date-parts":[[2023,5,15]],"date-time":"2023-05-15T17:50:57Z","timestamp":1684173057000},"page":"1-6","source":"Crossref","is-referenced-by-count":8,"title":["Investigation of Sub-20nm 4th generation DRAM cell transistor's parasitic resistance and scalable methodology for Sub-20nm era"],"prefix":"10.1109","author":[{"given":"Shinwoo","family":"Jeong","sequence":"first","affiliation":[{"name":"Samsung Electronics Co,DRAM Product &#x0026; Technology,Pyeongtaek,Korea,17786"}]},{"given":"Jin-Seong","family":"Lee","sequence":"additional","affiliation":[{"name":"Samsung Electronics Co,DRAM Product &#x0026; Technology,Pyeongtaek,Korea,17786"}]},{"given":"Jiuk","family":"Jang","sequence":"additional","affiliation":[{"name":"Samsung Electronics Co,DRAM Product &#x0026; Technology,Pyeongtaek,Korea,17786"}]},{"given":"Jooncheol","family":"Kim","sequence":"additional","affiliation":[{"name":"Samsung Electronics Co,DRAM Product &#x0026; Technology,Pyeongtaek,Korea,17786"}]},{"given":"Hyunsu","family":"Shin","sequence":"additional","affiliation":[{"name":"Samsung Electronics Co,DRAM Product &#x0026; Technology,Pyeongtaek,Korea,17786"}]},{"given":"Ji Hun","family":"Kim","sequence":"additional","affiliation":[{"name":"Samsung Electronics Co,DRAM Product &#x0026; Technology,Pyeongtaek,Korea,17786"}]},{"given":"Jeongwoo","family":"Song","sequence":"additional","affiliation":[{"name":"Samsung Electronics Co,DRAM Product &#x0026; Technology,Pyeongtaek,Korea,17786"}]},{"given":"Dongsoo","family":"Woo","sequence":"additional","affiliation":[{"name":"Samsung Electronics Co,DRAM Product &#x0026; Technology,Pyeongtaek,Korea,17786"}]},{"given":"Jeonghoon","family":"Oh","sequence":"additional","affiliation":[{"name":"Samsung Electronics Co,DRAM Product &#x0026; Technology,Pyeongtaek,Korea,17786"}]},{"given":"Jooyoung","family":"Lee","sequence":"additional","affiliation":[{"name":"Samsung Electronics Co,DRAM Product &#x0026; Technology,Pyeongtaek,Korea,17786"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2019.2947603"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2016.7495287"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1997.649477"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/SMICND.2004.1403001"},{"key":"ref11","author":"cho","year":"0","journal-title":"Innovative Indicator to Evaluate DRAM Cell Transistor Leakage Crrunt Distribution"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IWSOC.2005.78"},{"key":"ref2","article-title":"DDR5 standard specifications","year":"2022","journal-title":"Tech Rep JESD79-5B"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2015.7409774"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/SISPAD.1996.865256"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1971.17207"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.908882"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609344"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1063\/1.4906565"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2017.7936374"},{"key":"ref9","author":"taur","year":"1998","journal-title":"Fundamentals of Modern VLSI Devices"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1117\/12.920053"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00034"},{"key":"ref6","first-page":"125","article-title":"Crosstalk in Deep Submicron DRAMs","author":"yang","year":"2000","journal-title":"Rec IEEE Int Workshop Memory Technol Design Testing"},{"key":"ref5","article-title":"Fast and Efficient Offset Compensation by Noise-Aware Pre-charge and Operation of DRAM Bit Line Sense Amplifier","author":"kim","year":"0","journal-title":"IEEE Transactions on Circuits and Systems II Express Briefs"}],"event":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","location":"Monterey, CA, USA","start":{"date-parts":[[2023,3,26]]},"end":{"date-parts":[[2023,3,30]]}},"container-title":["2023 IEEE International Reliability Physics Symposium (IRPS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10117589\/10117581\/10118270.pdf?arnumber=10118270","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,12]],"date-time":"2023-06-12T17:49:48Z","timestamp":1686592188000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10118270\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,3]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/irps48203.2023.10118270","relation":{},"subject":[],"published":{"date-parts":[[2023,3]]}}}