{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,28]],"date-time":"2026-01-28T21:32:00Z","timestamp":1769635920969,"version":"3.49.0"},"reference-count":56,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,4,14]],"date-time":"2024-04-14T00:00:00Z","timestamp":1713052800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,4,14]],"date-time":"2024-04-14T00:00:00Z","timestamp":1713052800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000774","name":"Defense Threat Reduction Agency","doi-asserted-by":"publisher","award":["HDTRA 1-18-1-0002"],"award-info":[{"award-number":["HDTRA 1-18-1-0002"]}],"id":[{"id":"10.13039\/100000774","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,4,14]]},"DOI":"10.1109\/irps48228.2024.10529460","type":"proceedings-article","created":{"date-parts":[[2024,5,16]],"date-time":"2024-05-16T17:21:48Z","timestamp":1715880108000},"page":"10C.3-1-10C.3-6","source":"Crossref","is-referenced-by-count":1,"title":["Charge Trapping in Irradiated 3D Devices and ICs (Invited)"],"prefix":"10.1109","author":[{"given":"En Xia","family":"Zhang","sequence":"first","affiliation":[{"name":"University of Central Florida,Department of Electrical and Computer Engineering,Orlando,FL,USA,32816"}]},{"given":"Shintaro","family":"Toguchi","sequence":"additional","affiliation":[{"name":"Microchip Technology Inc. FBGA BU,San Jose,CA,USA,95134"}]},{"given":"Zi Xiang","family":"Guo","sequence":"additional","affiliation":[{"name":"Vanderbilt University,Department of Electrical and Computer Engineering,Nashville,TN,USA,37235"}]},{"given":"Michael L.","family":"Alles","sequence":"additional","affiliation":[{"name":"Vanderbilt University,Department of Electrical and Computer Engineering,Nashville,TN,USA,37235"}]},{"given":"Ronald D.","family":"Schrimpf","sequence":"additional","affiliation":[{"name":"Vanderbilt University,Department of Electrical and Computer Engineering,Nashville,TN,USA,37235"}]},{"given":"Daniel M.","family":"Fleetwood","sequence":"additional","affiliation":[{"name":"Vanderbilt University,Department of Electrical and Computer Engineering,Nashville,TN,USA,37235"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2017.8268316"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19574.2021.9720671"},{"key":"ref3","volume-title":"2022 CEA LETI technical report","year":"2023"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2016.7573428"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510625"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2020.2972439"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2021.3059999"},{"key":"ref8","first-page":"3.2.1","article-title":"3D-stacked CAAC\u2013In\u2013Ga\u2013Zn oxide FETs with gate length of 72 nm","volume-title":"IEDM Tech. Dig.","author":"Oota"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/iedm19574.2021.9720666"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2019.2931614"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2023.3280432"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2023.3235648"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2021.3138020"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2013.2284599"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.1983.4333142"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2013.2259260"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2014.6831837"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2016.7573407"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2015.7223699"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1002\/0471749095"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1016\/0038-1101(87)90132-8"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1063\/1.332937"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1063\/1.99828"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/23.273482"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/23.488764"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2014.6831837"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/23.45373"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/23.488768"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2007.911423"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2013.2249093"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2009.2033919"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2016.2634538"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2021.3085341"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2022.3144911"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2013.2284636"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2017.2786140"},{"key":"ref37","volume-title":"CMOS VLSI Design-A Circuits and Systems Perspective","author":"Weste","year":"2015"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/23.340582"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/55.830975"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1063\/1.126214"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2014.2362918"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2008.2001040"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2020.2971861"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1063\/1.1641521"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2016.2611058"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1063\/1.2927306"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1143\/JJAP.50.091102"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/23.736501"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2004.839201"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2017.2705118"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2021.3076977"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1016\/j.nima.2022.166727"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2013.2255313"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2006.884351"},{"key":"ref55","first-page":"T10-5.1","article-title":"First demonstration of sub-12 nm $L_g$ gate last IGZO-TFTs with oxygen tunnel architecture for front gate devices","volume-title":"Sympos. VLSI Technol.","author":"Subhechha"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/tns.2023.3346825"}],"event":{"name":"2024 IEEE International Reliability Physics Symposium (IRPS)","location":"Grapevine, TX, USA","start":{"date-parts":[[2024,4,14]]},"end":{"date-parts":[[2024,4,18]]}},"container-title":["2024 IEEE International Reliability Physics Symposium (IRPS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10529283\/10529298\/10529460.pdf?arnumber=10529460","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,5,17]],"date-time":"2024-05-17T05:12:53Z","timestamp":1715922773000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10529460\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,4,14]]},"references-count":56,"URL":"https:\/\/doi.org\/10.1109\/irps48228.2024.10529460","relation":{},"subject":[],"published":{"date-parts":[[2024,4,14]]}}}