{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,22]],"date-time":"2025-03-22T08:41:34Z","timestamp":1742632894795,"version":"3.28.0"},"reference-count":49,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/isca.2002.1003568","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T20:30:39Z","timestamp":1056573039000},"page":"123-134","source":"Crossref","is-referenced-by-count":73,"title":["SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint\/recovery"],"prefix":"10.1109","author":[{"given":"D.J.","family":"Sorin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.M.K.","family":"Martin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.D.","family":"Hill","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.A.","family":"Wood","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","article-title":"The Quality and Reliability of Intel's Quarter Micron Process","author":"seshan","year":"1998","journal-title":"Intel Technology Journal"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1984.1659214"},{"journal-title":"Fault-Tolerant Computer System Design","year":"1996","author":"pradhan","key":"ref33"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/71.730527"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/50202.50214"},{"key":"ref30","article-title":"Software and Hardware for Exploiting Speculative Parallelism with a Multiprocessor","author":"oplinger","year":"1997","journal-title":"Technical Report CSL-TR-97&#x2013;715"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1999.781037"},{"key":"ref36","article-title":"Alpha Particles Worry IC Makers as Device Features Keep Shrinking","author":"robertson","year":"1998","journal-title":"Semiconductor Business News"},{"key":"ref35","first-page":"25","article-title":"Transient fault detection via simultaneous multithreading","author":"reinhardt","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref34","first-page":"199","article-title":"Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap between Memory Consistency Models","author":"ranganathan","year":"1997","journal-title":"Proceedings of the ACM Symposium on Parallel Algorithms and Architectures"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/4.391126"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1984.1659216"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"ref2","first-page":"30","article-title":"Evaluating Non-deterministic Multi-threaded Commercial Workloads","author":"alameldeen","year":"2002","journal-title":"Proceedings of the Fifth Workshop on Computer Architecture Evaluation Using Commercial Workloads"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1990.89338"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1998.650559"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/70082.68187"},{"key":"ref21","first-page":"41","article-title":"Reining in Complexity","author":"grohoski","year":"1998","journal-title":"IEEE Computer"},{"key":"ref24","first-page":"170","article-title":"A General Purpose Cache-Aided Rollback Error Recovery (CARER) Technique","author":"hunt","year":"1987","journal-title":"Proceedings of the 17th International Symposium on Fault-Tolerant Computing Systems"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1147\/rd.261.0012"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1991.146709"},{"journal-title":"IEEE Standard for Scalable Coherent Interface (SCI)","year":"1993","key":"ref25"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/40.653032"},{"key":"ref11","doi-asserted-by":"crossref","DOI":"10.1145\/342001.363382","article-title":"Architectural Support for Scalable Speculative Parallelization in Shared-Memory Systems","author":"cintra","year":"2000","journal-title":"Proceedings of the 27th annual international symposium on Computer architecture"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1147\/rd.435.0863"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CONECT.1994.765349"},{"key":"ref13","article-title":"A White Paper on the Benefits of Chipkill-Correct ECC for PC Server Main Memory","author":"dell","year":"1997","journal-title":"IBM Microelectronics Division"},{"journal-title":"Interconnection Networks","year":"1997","author":"duato","key":"ref14"},{"key":"ref15","article-title":"A Survey of Rollback-Recovery Protocols in Message-Passing Systems","author":"elnozahy","year":"1996","journal-title":"Technical Report CMU-CS-96&#x2013;181"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/12.142678"},{"key":"ref17","first-page":"164","article-title":"Tightly Coupled Multiprocessor System Speeds Memory-access Times","volume":"57","author":"frank","year":"1984","journal-title":"Electronics"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/40.566196"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/307338.300993"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809458"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1080\/00207218808945198"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/277851.277897"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/12.543705"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1995.499187"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/2.17"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1147\/rd.401.0003"},{"key":"ref9","article-title":"Dynamic Verification of Cache Coherence Protocols","author":"cantin","year":"2001","journal-title":"Workshop on Memory Performance Issues"},{"key":"ref46","first-page":"24","article-title":"The SPLASH-2 programs: characterization and methodological considerations","author":"woo","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"ref45","first-page":"208","article-title":"The Stratus Computer System","author":"wilson","year":"1985","journal-title":"Resilient Computer Systems"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/71.80134"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/54.57906"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379247"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1998.650541"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1995.466999"},{"key":"ref43","first-page":"40","article-title":"Increasing Work, Pushing the Clock","author":"tremblay","year":"1998","journal-title":"IEEE Computer"}],"event":{"name":"29th Annual International Symposium on Computer Architecture","acronym":"ISCA-02","location":"Anchorage, AK, USA"},"container-title":["Proceedings 29th Annual International Symposium on Computer Architecture"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/7869\/21664\/01003568.pdf?arnumber=1003568","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T22:38:56Z","timestamp":1497566336000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1003568\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":49,"URL":"https:\/\/doi.org\/10.1109\/isca.2002.1003568","relation":{},"subject":[]}}