{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,16]],"date-time":"2026-03-16T10:10:58Z","timestamp":1773655858190,"version":"3.50.1"},"reference-count":33,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/isca.2003.1206985","type":"proceedings-article","created":{"date-parts":[[2004,3,22]],"date-time":"2004-03-22T09:34:28Z","timestamp":1079948068000},"page":"14-25","source":"Crossref","is-referenced-by-count":8,"title":["Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor"],"prefix":"10.1109","author":[{"given":"G.","family":"Magklis","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.L.","family":"Scott","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.","family":"Semeraro","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.H.","family":"Albonesi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Dropsho","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/195473.195549"},{"key":"ref32","article-title":"Scheduling for Reduced CPU Energy","author":"weiser","year":"1994","journal-title":"Proceedings of the 2nd USENIX Symposium on Operating Systems Design and Implementation"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ARVLSI.1997.634845"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2002.995696"},{"key":"ref10","article-title":"Adapting Processor Supply Voltage to Instruction-Level Parallelism","author":"childers","year":"2001","journal-title":"In Proceedings of the Kool Chips Workshop in conjunction with MICRO-34"},{"key":"ref11","article-title":"Circuit Design of XScaleTM Microprocessors","author":"clark","year":"2001","journal-title":"In 2001 Symposium on VLSI Circuits Short Course on Physical Design for Low-Power and High-Performance Microprocessor Circuits"},{"key":"ref12","author":"ellis","year":"1985","journal-title":"A Compiler for VLIW Architectures Technical Report YALEU\/DCS\/RR-364"},{"key":"ref13","article-title":"ATOM: A Flexible Interface for Building High Performance Program Analysis Tools","author":"eustace","year":"1995","journal-title":"Proc 1995 USENIX Tech Conf"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/545214.545222"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379253"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1981.1675827"},{"key":"ref17","article-title":"Crusoe Power Management &#x2013; Reducing the Operating Power with LongRun","author":"fleischmann","year":"2000","journal-title":"In Proceedings of the HOT CHIPS Symposium XII"},{"key":"ref18","article-title":"Transmeta breaks x86 low power barrier","volume":"14","author":"halfhill","year":"2000","journal-title":"Microprocessor Report"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/2.869367"},{"key":"ref28","article-title":"Evaluating Design Tradeoffs in Dual Speed Pipelines","author":"pyreddy","year":"2001","journal-title":"In Proceedings of the Workshop on Complexity-Effective Design in conjunction with ISCA-28"},{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.1109\/ISCA.2000.854380","article-title":"Wamonospacech: A Framework for Architectural-Level Power Analysis and Optimizations","author":"brooks","year":"2000","journal-title":"Proc 27th Int Symp Computer Architecture"},{"key":"ref27","year":"2002","journal-title":"Intel Corp Datasheet Intel&#x00AE; Pentium&#x00AE; 4 Processor with 512-KB L2 cache on 0 13 Micron Process at 2 GHz&#x2013;3 06 GHz"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"46","DOI":"10.1109\/MICRO.1996.566449","article-title":"Efficient Path Profiling","author":"ball","year":"1996","journal-title":"In Proceedings of the 29th Annual IEEE\/ACM International Symposium on Microarchitecture"},{"key":"ref6","article-title":"An Adaptive Issue Queue for Reduced Power at High Performance","author":"buyuktosunoglu","year":"2000","journal-title":"In Proceedings of the Workshop on Power-Aware Computer Systems in conjunction with ASPLOS-IX"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176263"},{"key":"ref5","author":"burger","year":"1997","journal-title":"The SimpleScalar Tool Set Version 2 0 Technical Report CS-TR-97-1342"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1988.639244"},{"key":"ref7","article-title":"Dynamic Instruction Scheduling Slack","author":"casmira","year":"2000","journal-title":"Proceedings of the Kool Chips Workshop in Conjunction with MICRO-33"},{"key":"ref2","first-page":"245","article-title":"Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures","author":"balasubramonian","year":"2000","journal-title":"In Proceedings of the 33rd Annual IEEE\/ACM International Symposium on Microarchitecture"},{"key":"ref9","author":"chapiro","year":"1984","journal-title":"Globally asynchronous locally synchronous systems"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"85","DOI":"10.1145\/258915.258924","article-title":"Exploiting Hardware Performance Counters with Flow and Context Sensitive Profiling","author":"ammons","year":"1997","journal-title":"Proc of the 1997 ACM SIGPLAN Conference on Programming Language Design and Implementation"},{"key":"ref20","article-title":"Compiler-Directed Dynamic Frequency and Voltage Scaling","author":"hsu","year":"2000","journal-title":"In Proceedings of the Workshop on Power-Aware Computer Systems in conjunction with ASPLOS-IX"},{"key":"ref22","article-title":"The Coign Automatic Distributed Partitioning System","author":"hunt","year":"1999","journal-title":"Proceedings of the 2nd USENIX Symposium on Operating Systems Design and Implementation"},{"key":"ref21","article-title":"Profile-Based Energy Reduction in High-Performance Processors","author":"huang","year":"2001","journal-title":"Proc 4th ACM Workshop on Feedback-Directed and Dynamic Optimization (FDDO-4)"},{"key":"ref24","first-page":"330","article-title":"Media-bench: a Tool for Evaluating and Synthesizing Multimedia and Communications Systems","author":"lee","year":"1997","journal-title":"In Proceedings of the 30th Annual IEEE\/ACM International Symposium on Microarchitecture"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003573"},{"key":"ref26","article-title":"On the Use of Microarchitecture-Driven Dynamic Voltage Scaling","author":"marculescu","year":"2000","journal-title":"In Proceedings of the Workshop on Complexity-Effective Design in conjunction with ISCA-27"},{"key":"ref25","first-page":"7","volume":"14","author":"leibson","year":"2000","journal-title":"XScale (StrongArm-2) Muscles In Microprocessor Report"}],"event":{"name":"ISCA 2003: 30th International Symposium on Computer Architecture","location":"San Diego, CA, USA","acronym":"ISCA-03"},"container-title":["30th Annual International Symposium on Computer Architecture, 2003. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8578\/27165\/01206985.pdf?arnumber=1206985","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T00:25:55Z","timestamp":1497572755000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1206985\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":33,"URL":"https:\/\/doi.org\/10.1109\/isca.2003.1206985","relation":{},"subject":[]}}