{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T08:46:02Z","timestamp":1729673162097,"version":"3.28.0"},"reference-count":44,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/isca.2003.1207013","type":"proceedings-article","created":{"date-parts":[[2004,3,22]],"date-time":"2004-03-22T14:34:28Z","timestamp":1079966068000},"page":"350-361","source":"Crossref","is-referenced-by-count":1,"title":["Virtual simple architecture (VISA): exceeding the complexity limit in safe real-time systems"],"prefix":"10.1109","author":[{"family":"Aravindh Anantaraman","sequence":"first","affiliation":[]},{"family":"Kiran Seth","sequence":"additional","affiliation":[]},{"family":"Kaustubh Patil","sequence":"additional","affiliation":[]},{"given":"E.","family":"Rotenberg","sequence":"additional","affiliation":[]},{"given":"F.","family":"Mueller","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/RTTAS.1997.601358"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1023\/A:1011132221066"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1007\/BF00571421"},{"key":"ref32","article-title":"Is worst-case execution-time analysis a non-problem? &#x2014; towards new software and hardware architectures","author":"puschner","year":"2002","journal-title":"2nd EuroMicro Int'l Workshop on WCET Analysis"},{"key":"ref31","article-title":"Computing maximum task execution times - a graph-based approach","volume":"9","author":"puschner","year":"1997","journal-title":"Real-Time Systems"},{"journal-title":"Zeitanalyse von Echtzeitprogrammen","year":"1993","author":"puschner","key":"ref30"},{"key":"ref37","doi-asserted-by":"crossref","DOI":"10.1109\/ISCA.1995.524578","article-title":"Simultaneous Multi-threading: Maximizing On-Chip Parallelism","author":"tullsen","year":"1995","journal-title":"22nd Int'l Symp on Computer Architecture"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/REAL.1998.739739"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2001.991103"},{"journal-title":"Static analysis of cache analysis for real-time programming","year":"1995","author":"rawat","key":"ref34"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/REAL.1992.242675"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008190423977"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/12.743411"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/REAL.1995.495218"},{"key":"ref13","doi-asserted-by":"crossref","DOI":"10.1109\/MICRO.2001.991123","article-title":"Saving Energy with Architectural and Frequency Adaptations for Multimedia Applications","author":"hughes","year":"2001","journal-title":"34th Int'l Symp on Microarchitecture"},{"key":"ref14","article-title":"Worst case timing analysis of RISC processors: R3000\/R3010 case study","author":"hur","year":"1995","journal-title":"Real-Time Systems Symposium"},{"key":"ref15","article-title":"Efficient worst case timing analysis of data caching","author":"kim","year":"1996","journal-title":"Real-Time Technology and Applications Symposium"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/REAL.1995.495219"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/REAL.1996.563722"},{"key":"ref18","article-title":"An accurate worst case timing analysis for RISC processors","author":"lim","year":"1994","journal-title":"Real-Time Systems Symp"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/321738.321743"},{"key":"ref28","article-title":"Architecture and O\/S support for predictable real-time systems","author":"niehaus","year":"1992","journal-title":"Spring internal document"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/44.6.531"},{"key":"ref27","article-title":"Predicting instruction cache behavior","author":"mueller","year":"1994","journal-title":"Proc of the ACM SIGPLAN Workshop on Language Compiler and Tool Support for Real-Time Systems"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809458"},{"key":"ref6","article-title":"Evaluating future microprocessors: The simplescalar toolset","author":"burger","year":"1996","journal-title":"Tech Rep CS-TR-96-1308"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1007\/BF01088696"},{"key":"ref5","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref8","article-title":"On hardware and hardware models for embedded real-time systems","author":"engblom","year":"2001","journal-title":"Proc IEEE Real-Time Embedded Syst Workshop"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/EURMIC.1998.711807"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/REAL.1994.342718"},{"key":"ref9","first-page":"57","article-title":"Real-time systems need predictability","author":"hand","year":"1989","journal-title":"Computer Design (RISC Supplement)"},{"journal-title":"Bounding instruction cache performance","year":"1996","author":"arnold","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008138407139"},{"key":"ref22","article-title":"A Framework to Model Branch Prediction for WCET Analysis","author":"mitra","year":"2002","journal-title":"2nd Workshop on Worst Case Execution Time Analysis (WCET)"},{"key":"ref21","article-title":"Combining branch predictors","author":"mcfarling","year":"1993","journal-title":"Technical Report TN-36 WRL"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1007\/BF01088834"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/EMWRTS.1997.613765"},{"key":"ref41","article-title":"Increasing Superscalar Performance through Multistreaming","author":"yamamoto","year":"1995","journal-title":"Parallel Architectures and Compilation Techniques"},{"journal-title":"Static cache simulation and its applications","year":"1994","author":"mueller","key":"ref23"},{"year":"0","key":"ref44","article-title":"C-lab: WCET Benchmarks"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008145215849"},{"year":"0","key":"ref43"},{"key":"ref25","first-page":"29","article-title":"Timing predictions for multi-level caches","author":"mueller","year":"1997","journal-title":"ACM SIGPLAN Workshop on Language Compiler and Tool Support for Real-Time Systems"}],"event":{"name":"ISCA 2003: 30th International Symposium on Computer Architecture","acronym":"ISCA-03","location":"San Diego, CA, USA"},"container-title":["30th Annual International Symposium on Computer Architecture, 2003. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8578\/27165\/01207013.pdf?arnumber=1207013","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T04:25:55Z","timestamp":1497587155000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1207013\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":44,"URL":"https:\/\/doi.org\/10.1109\/isca.2003.1207013","relation":{},"subject":[]}}