{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,25]],"date-time":"2026-10-25T19:39:56Z","timestamp":1792957196362,"version":"4.5.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/isca.2004.1310760","type":"proceedings-article","created":{"date-parts":[[2004,11,12]],"date-time":"2004-11-12T19:14:14Z","timestamp":1100286854000},"page":"14-25","source":"Crossref","is-referenced-by-count":21,"title":["Evaluating the imagine stream architecture"],"prefix":"10.1109","author":[{"family":"Jung Ho Ahn","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"W.J.","family":"Dally","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"B.","family":"Khailany","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"U.J.","family":"Kapasi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"A.","family":"Das","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859665"},{"key":"16","year":"0","journal-title":"TMS320C6713 Floating-Point Digital Signal Processors 2003 03 Edition"},{"key":"13","author":"rixner","year":"2001","journal-title":"Stream Processor Architecture"},{"key":"14","first-page":"324","article-title":"A 0.18?m CMOS IA32 microprocessor with a 4GHz integer execution unit","author":"sager","year":"2001","journal-title":"2007 IEEE International Solid-State Circuits Conference Digest of Technical Papers"},{"key":"11","author":"rai","year":"2003","journal-title":"A Feasibility Study on the Application of Stream Architectures for Packet Processing Applications"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2002.1187061"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/1048935.1050187"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2003.1213417"},{"key":"1","article-title":"RT_STAP: Real-time space-time adaptive processing benchmark","author":"cain","year":"1997","journal-title":"Technical Report MTR 96B0000021"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/383259.383275"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1220582"},{"key":"6","article-title":"Stream scheduling","volume":"122","author":"kapasi","year":"2002","journal-title":"Concurrent VLSI Architecture Tech Report"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.1996.517074"},{"key":"4","year":"0","journal-title":"Intel Pentium M Processor"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379005"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/40.918001"}],"event":{"name":"Proceedings. 31st Annual International Symposium on Computer Architecture, 2004.","location":"Munchen, Germany"},"container-title":["Proceedings. 31st Annual International Symposium on Computer Architecture, 2004."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9170\/29103\/01310760.pdf?arnumber=1310760","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T14:10:47Z","timestamp":1489500647000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1310760\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/isca.2004.1310760","relation":{},"subject":[]}}