{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,13]],"date-time":"2025-11-13T18:07:20Z","timestamp":1763057240429,"version":"3.28.0"},"reference-count":26,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/isca.2004.1310765","type":"proceedings-article","created":{"date-parts":[[2004,11,13]],"date-time":"2004-11-13T00:14:14Z","timestamp":1100304854000},"page":"76-87","source":"Crossref","is-referenced-by-count":25,"title":["Microarchitecture optimizations for exploiting memory-level parallelism"],"prefix":"10.1109","author":[{"family":"Yuan Chou","sequence":"first","affiliation":[]},{"given":"B.","family":"Fahs","sequence":"additional","affiliation":[]},{"given":"S.","family":"Abraham","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","article-title":"A day in the life of a data cache miss","author":"karkhanis","year":"2002","journal-title":"Workshop on Memory Performance Issues"},{"key":"17","doi-asserted-by":"crossref","DOI":"10.1145\/605397.605415","article-title":"Design and evaluation of compiler algorithms for pre-execution","author":"kim","year":"2002","journal-title":"ASPLOS-X"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645819"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937427"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379250"},{"journal-title":"The SPARC Architecture Manual","year":"1994","author":"weaver","key":"13"},{"year":"0","key":"14"},{"key":"11","article-title":"Speculative execution based on value prediction","volume":"1080","author":"gabbay","year":"1996","journal-title":"department technical report"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645815"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903250"},{"key":"20","doi-asserted-by":"crossref","DOI":"10.1109\/MICRO.2003.1253246","article-title":"Checkpoint processing and recovery: Towards scalable large instruction window processors","author":"akkary","year":"2003","journal-title":"36th International Symposium on Microarchitecture"},{"key":"22","doi-asserted-by":"crossref","DOI":"10.1145\/377792.377856","article-title":"Slice-processors: An implementation of operation-based prediction","author":"moshovos","year":"2001","journal-title":"International Conference on Supercomputing"},{"key":"23","article-title":"Assisted execution","volume":"98","author":"dubois","year":"1998","journal-title":"Technical report Univ of Southern California"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694797"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1997.569611"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1145\/291069.291067"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253191"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694758"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237173"},{"key":"1","article-title":"Contrasting characteristics and cache performance of technical and multi-user commercial workloads","author":"maynard","year":"1998","journal-title":"ASPLOS-VI"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/782814.782859"},{"key":"6","article-title":"Code transformations to improve memory parallelism","author":"pai","year":"1999","journal-title":"32nd International Symposium on Microarchitecture"},{"key":"5","article-title":"MLP yes! ILP no!","author":"glew","year":"1998","journal-title":"ASPLOS Wild and Crazy Idea Session'98"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183532"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/263580.263597"}],"event":{"name":"Proceedings. 31st Annual International Symposium on Computer Architecture, 2004.","location":"Munchen, Germany"},"container-title":["Proceedings. 31st Annual International Symposium on Computer Architecture, 2004."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9170\/29103\/01310765.pdf?arnumber=1310765","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,4,30]],"date-time":"2023-04-30T05:48:22Z","timestamp":1682833702000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1310765\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/isca.2004.1310765","relation":{},"subject":[]}}