{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T05:41:13Z","timestamp":1729662073294,"version":"3.28.0"},"reference-count":25,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/isca.2004.1310778","type":"proceedings-article","created":{"date-parts":[[2004,11,12]],"date-time":"2004-11-12T19:14:14Z","timestamp":1100286854000},"page":"238-249","source":"Crossref","is-referenced-by-count":3,"title":["From sequences of dependent instructions to functions : an approach for improving performance without ilp or speculation"],"prefix":"10.1109","author":[{"given":"S.","family":"Yehia","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"O.","family":"Temam","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"19","DOI":"10.1145\/859618.859667"},{"doi-asserted-by":"publisher","key":"17","DOI":"10.1109\/MICRO.1994.717456"},{"doi-asserted-by":"publisher","key":"18","DOI":"10.1145\/201059.201065"},{"doi-asserted-by":"publisher","key":"15","DOI":"10.1109\/MICRO.2000.898080"},{"doi-asserted-by":"publisher","key":"16","DOI":"10.1109\/12.272427"},{"doi-asserted-by":"publisher","key":"13","DOI":"10.1109\/ISCA.1998.694786"},{"doi-asserted-by":"publisher","key":"14","DOI":"10.1109\/12.931895"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1109\/92.831434"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.1109\/MICRO.2001.991104"},{"doi-asserted-by":"publisher","key":"21","DOI":"10.1109\/12.48865"},{"key":"20","doi-asserted-by":"crossref","first-page":"238","DOI":"10.1109\/MICRO.1996.566465","article-title":"The performance potential of data dependence speculation & collapsing","author":"sazeides","year":"1996","journal-title":"Proceedings of the 29th Annual IEEE\/ACM International Symposium on Microarchitecture"},{"doi-asserted-by":"publisher","key":"22","DOI":"10.1145\/106972.106991"},{"key":"23","first-page":"225","article-title":"CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit","author":"ye","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"24","doi-asserted-by":"crossref","first-page":"95","DOI":"10.1145\/329166.329187","article-title":"A C compiler for a processor with a reconfigurable functional unit","author":"ye","year":"2000","journal-title":"Proceedings of the 2000 ACM\/SIGDA Eighth International Symposium on Field Programmable Gate Arrays"},{"key":"25","article-title":"Optimal logarithmic adder structures with a fanout of two for minimizing the areadelay product","author":"ziegler","year":"2001","journal-title":"International Symposium on Circuits and Systems"},{"key":"3","article-title":"Evaluating future microprocessors: The SimpleScalar tool set","volume":"cs tr 1996 1308","author":"burger","year":"1996","journal-title":"Technical Report"},{"key":"2","article-title":"Virtex-II pro platform FPGAs: Functional description","volume":"ds083 2","year":"2002","journal-title":"Technical Report"},{"key":"10","article-title":"MiBench: A free, commercially representative embedded benchmark suite","author":"guthaus","year":"2001","journal-title":"Proceedings of the IEEE 4th Annual Workshop on Workload Characterization"},{"year":"1998","journal-title":"Alpha Architecture Handbook","key":"1"},{"key":"7","article-title":"Performance characterization of a hardware framework for dynamic optimization","author":"fahs","year":"2001","journal-title":"Proceedings of the 34th Annual IEEE\/ACM International Symposium on Microarchitecture"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1145\/508352.508353"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1109\/MICRO.2003.1253189"},{"key":"4","doi-asserted-by":"crossref","first-page":"147","DOI":"10.1145\/360128.360144","article-title":"PipeRench implementation of the instruction path coprocessor","author":"chou","year":"2000","journal-title":"Proceedings of the 33rd annual ACM\/IEEE international symposium on Microarchitecture"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1145\/581630.581635"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/MICRO.1998.742769"}],"event":{"name":"Proceedings. 31st Annual International Symposium on Computer Architecture, 2004.","location":"Munchen, Germany"},"container-title":["Proceedings. 31st Annual International Symposium on Computer Architecture, 2004."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9170\/29103\/01310778.pdf?arnumber=1310778","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,12,21]],"date-time":"2018-12-21T04:27:44Z","timestamp":1545366464000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1310778\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/isca.2004.1310778","relation":{},"subject":[]}}