{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,5]],"date-time":"2026-08-05T17:53:19Z","timestamp":1785952399933,"version":"3.56.0"},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/isca.2004.1310786","type":"proceedings-article","created":{"date-parts":[[2004,11,12]],"date-time":"2004-11-12T19:14:14Z","timestamp":1100286854000},"page":"338-349","source":"Crossref","is-referenced-by-count":116,"title":["A first-order superscalar processor model"],"prefix":"10.1109","author":[{"given":"T.S.","family":"Karkhanis","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"J.E.","family":"Smith","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"17","doi-asserted-by":"crossref","first-page":"404","DOI":"10.1145\/17356.17403","article-title":"Optimal pipelining in supercomputers","author":"kunkel","year":"1986","journal-title":"International Symposium on Computer Architecture"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003558"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1972.223514"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/12.40844"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253198"},{"key":"14","author":"ofelt","year":"1999","journal-title":"Efficient Performance Prediction for Modern Microprocessors"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1997.569691"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694797"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003557"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1987.1676981"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/30350.30354"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2000.842273"},{"key":"7","doi-asserted-by":"crossref","DOI":"10.1023\/A:1026431920605","article-title":"An exploration of instruction fetch requirement in out-of-order superscalar processors","volume":"29","author":"michaud","year":"2001","journal-title":"International Journal of Parallel Programming"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.1999.807388"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1994.717410"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003559"},{"key":"9","article-title":"Modeling superscalar processors via statistical simulation","author":"carl","year":"1998","journal-title":"Workshop on Performance Analysis and its Impact on Design"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2001.953284"}],"event":{"name":"Proceedings. 31st Annual International Symposium on Computer Architecture, 2004.","location":"Munchen, Germany"},"container-title":["Proceedings. 31st Annual International Symposium on Computer Architecture, 2004."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9170\/29103\/01310786.pdf?arnumber=1310786","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T07:52:01Z","timestamp":1497599521000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1310786\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/isca.2004.1310786","relation":{},"subject":[]}}