{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:14:52Z","timestamp":1763468092923,"version":"3.41.0"},"reference-count":53,"publisher":"IEEE","license":[{"start":{"date-parts":[[2012,6,1]],"date-time":"2012-06-01T00:00:00Z","timestamp":1338508800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2012,6,1]],"date-time":"2012-06-01T00:00:00Z","timestamp":1338508800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,6]]},"DOI":"10.1109\/isca.2012.6237004","type":"proceedings-article","created":{"date-parts":[[2012,7,21]],"date-time":"2012-07-21T00:59:02Z","timestamp":1342832342000},"page":"37-48","source":"Crossref","is-referenced-by-count":139,"title":["Towards energy-proportional datacenter memory with mobile DRAM"],"prefix":"10.1109","author":[{"given":"Krishna T.","family":"Malladi","sequence":"first","affiliation":[{"name":"Electrical Engineering, Stanford University, USA"}]},{"given":"Frank A.","family":"Nothaft","sequence":"additional","affiliation":[{"name":"Electrical Engineering, Stanford University, USA"}]},{"given":"Karthika","family":"Periyathambi","sequence":"additional","affiliation":[{"name":"Electrical Engineering, Stanford University, USA"}]},{"given":"Benjamin C.","family":"Lee","sequence":"additional","affiliation":[{"name":"Electrical and Computer Engineering, Duke University, USA"}]},{"given":"Christos","family":"Kozyrakis","sequence":"additional","affiliation":[{"name":"Electrical Engineering, Stanford University, USA"}]},{"given":"Mark","family":"Horowitz","sequence":"additional","affiliation":[{"name":"Electrical Engineering, Stanford University, USA"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654102"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854314"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2007.443"},{"article-title":"Characterization of Apache web server with Specweb 2005","volume-title":"MEDEA","author":"Bosque","key":"ref4"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1147\/rd.144.0402"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1998582.1998590"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903260"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1961296.1950392"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1273440.1250699"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/lpe.2001.945388"},{"article-title":"FB DIMM memory architectures: Understanding mechanisms, overheads, & scaling","volume-title":"HPCA","author":"Ganesh","key":"ref11"},{"volume-title":"Cost of power in large-scale data centers","author":"Hamilton","key":"ref12"},{"key":"ref13","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-642-24322-6_20","article-title":"What computer architects need to know about memory throttling","volume-title":"WEED","author":"Hanson"},{"volume-title":"DDR3 memory technology. Technology brief TC100202TB, Hewlett-Packard","year":"2010","key":"ref14"},{"volume-title":"The Datacenter as a Computer. Morgan and Claypool","year":"2009","author":"Hoelzle","key":"ref15"},{"volume-title":"HP. CACTI 5.1","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1077603.1077696"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2008.4658648"},{"volume-title":"Memory Systems: Cache, DRAM, Disk","year":"2007","author":"Jacob","key":"ref19"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815971"},{"volume-title":"JEDEC standard for LP-DDR2. Standard JESD209\u20132B, JEDEC","year":"2010","key":"ref21"},{"volume-title":"MICRO","key":"ref22","article-title":"Thread cluster memory scheduling: Exploiting differences in memory access behavior"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.73"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/356989.356999"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.37"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555789"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1064978.1065034"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/1508284.1508269"},{"key":"ref29","article-title":"Startup SeaMicro packs 512 Intel Atoms in server","author":"Merritt","year":"2010","journal-title":"EE Times"},{"volume-title":"Calculating memory system power for DDR2. Technical Note tn4704, Micron","year":"2005","key":"ref30"},{"volume-title":"Calculating memory system power for DDR3. Technical Note TN-41\u201301, Micron","year":"2007","key":"ref31"},{"volume-title":"152-ball x32 mobile lpddr pop (ti-omap). Data Sheet MT46HxxxMxxLxCG, Micron","year":"2008","key":"ref32"},{"volume-title":"Micron 2Gb: x4, x8, x16 DDR3 SDRAM. Data Sheet MT41J128M16HA-125, Micron","year":"2010","key":"ref33"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/1713254.1713276"},{"article-title":"A 4.3GB\/s mobile memory interface with power-efficient bandwidth scaling","volume-title":"VLSI","author":"Palmer","key":"ref35"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598120"},{"volume-title":"Mobile XDR memory versus LPDDR2","key":"ref37"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1816002"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555801"},{"key":"ref40","article-title":"Scaling memcached at Facebook","author":"Saab","year":"2008","journal-title":"Facebook Engineering Note"},{"key":"ref41","doi-asserted-by":"crossref","DOI":"10.1109\/MICRO.2010.20","article-title":"The ZCache: Decoupling ways and associativity","volume-title":"MICRO","author":"Sanchez"},{"key":"ref42","article-title":"Signal and power integrity limitations for mobile memory in 3D packaging","author":"Schmitt","year":"2010","journal-title":"EE Times"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/1961296.1950389"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-93799-9_2"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/2024723.2000099"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.177"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815983"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.42"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2006.4380850"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/1735971.1736064"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.66"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771792"}],"event":{"name":"2012 ACM\/IEEE 39th International Symposium on Computer Architecture (ISCA)","start":{"date-parts":[[2012,6,9]]},"location":"Portland, OR, USA","end":{"date-parts":[[2012,6,13]]}},"container-title":["2012 39th Annual International Symposium on Computer Architecture (ISCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6230820\/6236993\/06237004.pdf?arnumber=6237004","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T06:22:17Z","timestamp":1747808537000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6237004\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,6]]},"references-count":53,"URL":"https:\/\/doi.org\/10.1109\/isca.2012.6237004","relation":{},"subject":[],"published":{"date-parts":[[2012,6]]}}}