{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:03:29Z","timestamp":1761581009701,"version":"3.41.0"},"reference-count":25,"publisher":"IEEE","license":[{"start":{"date-parts":[[2012,6,1]],"date-time":"2012-06-01T00:00:00Z","timestamp":1338508800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2012,6,1]],"date-time":"2012-06-01T00:00:00Z","timestamp":1338508800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,6]]},"DOI":"10.1109\/isca.2012.6237028","type":"proceedings-article","created":{"date-parts":[[2012,7,21]],"date-time":"2012-07-21T00:59:02Z","timestamp":1342832342000},"page":"321-332","source":"Crossref","is-referenced-by-count":1,"title":["FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion"],"prefix":"10.1109","author":[{"given":"Jaewoong","family":"Sim","sequence":"first","affiliation":[{"name":"Georgia Institute of Technology, USA"}]},{"given":"Jaekyu","family":"Lee","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, USA"}]},{"given":"Moinuddin K.","family":"Qureshi","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, USA"}]},{"given":"Hyesoon","family":"Kim","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, USA"}]}],"member":"263","reference":[{"volume-title":"AMD Phenom $(TM)$II processor model","key":"ref1"},{"volume-title":"Macsim simulator","key":"ref2"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/633625.52409"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1150019.1136515"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2024723.2000075"},{"volume-title":"Intel Core i7 Processors","key":"ref6"},{"volume-title":"Intel\u278b Nehalem Microarchitecture","key":"ref7"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.52"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454145"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815971"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/384286.264213"},{"article-title":"Tradeoffs in two-level onchip caching","volume-title":"ISCA-16","author":"Jouppi","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.70816"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1999946.1999983"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2024723.2000111"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1273440.1250709"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/605432.605403"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"},{"article-title":"A new approach to cache management","volume-title":"MICRO-28","author":"Tyson","key":"ref19"},{"volume-title":"VIA C7 Processors","key":"ref20"},{"article-title":"Power-driven design of router microarchitectures in on-chip networks","volume-title":"MICRO-36","author":"Wang","key":"ref21"},{"article-title":"Orion: a power-performance simulator for interconnection networks","volume-title":"MICRO-35","author":"Wang","key":"ref22"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555778"},{"key":"ref24","first-page":"99","article-title":"Non-inclusion property in multi-level caches revisited","volume":"14","author":"Zahran","year":"2007","journal-title":"International Journal of Computers and Their Applications"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2004.1291359"}],"event":{"name":"2012 ACM\/IEEE 39th International Symposium on Computer Architecture (ISCA)","start":{"date-parts":[[2012,6,9]]},"location":"Portland, OR, USA","end":{"date-parts":[[2012,6,13]]}},"container-title":["2012 39th Annual International Symposium on Computer Architecture (ISCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6230820\/6236993\/06237028.pdf?arnumber=6237028","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T05:21:14Z","timestamp":1747804874000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6237028\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,6]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/isca.2012.6237028","relation":{},"subject":[],"published":{"date-parts":[[2012,6]]}}}