{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T04:08:40Z","timestamp":1747886920895,"version":"3.41.0"},"reference-count":27,"publisher":"IEEE","license":[{"start":{"date-parts":[[2012,6,1]],"date-time":"2012-06-01T00:00:00Z","timestamp":1338508800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2012,6,1]],"date-time":"2012-06-01T00:00:00Z","timestamp":1338508800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,6]]},"DOI":"10.1109\/isca.2012.6237034","type":"proceedings-article","created":{"date-parts":[[2012,7,21]],"date-time":"2012-07-21T00:59:02Z","timestamp":1342832342000},"page":"392-403","source":"Crossref","is-referenced-by-count":21,"title":["Buffer-on-board memory systems"],"prefix":"10.1109","author":[{"given":"Elliott","family":"Cooper-Balis","sequence":"first","affiliation":[{"name":"University of Maryland, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paul","family":"Rosenfeld","sequence":"additional","affiliation":[{"name":"University of Maryland, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bruce","family":"Jacob","sequence":"additional","affiliation":[{"name":"University of Maryland, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"article-title":"DDR3 Power Estimates, Affect of Bandwidth, and Comparisons to DDR2","volume-title":"Technical report","year":"2007","key":"ref1"},{"article-title":"Low-Power Fully Buffered DIMM","volume-title":"Whitepaper","year":"2007","key":"ref2"},{"article-title":"Netlist FBDIMM preliminary power analysis Training","volume-title":"Technical report","year":"2007","key":"ref3"},{"volume-title":"Datasheet","year":"2008","key":"ref4"},{"volume-title":"Technical report, Association, JEDEC Solid State Technology","year":"2010","key":"ref5"},{"article-title":"IBM Power 795 Technical Overview and Introduction","volume-title":"Datasheet","year":"2010","key":"ref6"},{"article-title":"Intel 7500 Scalable Memory Buffer","volume-title":"Technical report","year":"2010","key":"ref7"},{"key":"ref8","first-page":"41","article-title":"QEMU, a fast and portable dynamic translator","volume-title":"Proceedings of the annual conference on USENIX Annual Technical Conference, ATEC\u201905","author":"Bellard"},{"article-title":"PARSEC 2.0: A New Benchmark Suite for Chip-Multiprocessors","volume-title":"Proceedings of the 5th Annual Workshop on Modeling, Benchmarking and Simulation","author":"Bienia","key":"ref9"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765953"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/12.966491"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1353522.1353531"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TADVP.2009.2013818"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346190"},{"volume-title":"Memory Systems: Cache, DRAM, Disk","year":"2008","author":"Jacob","key":"ref15"},{"key":"ref16","article-title":"Micron rolls DDR3 LRDIMM","author":"LaPedus","year":"2009","journal-title":"EE Times"},{"key":"ref17","first-page":"19","article-title":"Memory bandwidth and machine balance in current high performance computers","author":"McCalpin","year":"1995","journal-title":"IEEE Computer Society Technical Committee on Computer Architecture (TCCA) Newsletter"},{"article-title":"MARSSx86: A Full System Simulator for x86 CPUs","volume-title":"Design Automation Conference 2011 (DAC\u201811)","author":"Patel","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"ref20","article-title":"AMD\u2019s Next Server Platform \u201cMaranello\u201d","author":"Shigehiro","year":"2008","journal-title":"PC Watch"},{"key":"ref21","article-title":"The AMD Memory Roadmap: DDR3, FBD and G3MX Examined","author":"Shimpi","year":"2007","journal-title":"AnandTech.com"},{"key":"ref22","article-title":"Prefetching vs The Memory System: Optimizations for Multi-Core Server Platforms","volume-title":"PhD thesis","author":"Srinivasan","year":"2007"},{"key":"ref23","article-title":"Enterprise X-Architecture 5th Generation","volume-title":"Technical report","author":"Suarez","year":"2010"},{"key":"ref24","article-title":"Modern DRAM Memory Systems: Performance Analysis and a High Performance, Power-Constrained DRAM Scheduling Algorithm","volume-title":"PhD thesis","author":"Wang","year":"2005"},{"journal-title":"DRAM and Memory System Trends","year":"2004","author":"Woo","key":"ref25"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2007.363733"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555788"}],"event":{"name":"2012 ACM\/IEEE 39th International Symposium on Computer Architecture (ISCA)","start":{"date-parts":[[2012,6,9]]},"location":"Portland, OR, USA","end":{"date-parts":[[2012,6,13]]}},"container-title":["2012 39th Annual International Symposium on Computer Architecture (ISCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6230820\/6236993\/06237034.pdf?arnumber=6237034","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T06:26:00Z","timestamp":1747808760000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6237034\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,6]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/isca.2012.6237034","relation":{},"subject":[],"published":{"date-parts":[[2012,6]]}}}