{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,19]],"date-time":"2025-12-19T09:28:31Z","timestamp":1766136511900},"reference-count":49,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,6]]},"DOI":"10.1109\/isca.2014.6853215","type":"proceedings-article","created":{"date-parts":[[2014,7,29]],"date-time":"2014-07-29T19:19:17Z","timestamp":1406661557000},"page":"217-228","source":"Crossref","is-referenced-by-count":3,"title":["HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs"],"prefix":"10.1109","author":[{"given":"Simone","family":"Campanoni","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kevin","family":"Brownell","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Svilen","family":"Kanev","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Timothy M.","family":"Jones","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gu-Yeon","family":"Wei","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Brooks","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"35","doi-asserted-by":"publisher","DOI":"10.1145\/980152.980156"},{"key":"36","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237144"},{"key":"33","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736055"},{"key":"39","doi-asserted-by":"publisher","DOI":"10.1145\/1082469.1082471"},{"key":"37","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2009.9"},{"key":"38","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1995.524580"},{"key":"43","doi-asserted-by":"publisher","DOI":"10.1145\/1542476.1542496"},{"key":"42","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2005.24"},{"key":"41","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"},{"key":"40","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2002.995699"},{"key":"22","article-title":"A controllable MIMD architecture","author":"lundstrom","year":"1986","journal-title":"Advanced Computer Architecture"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859640"},{"journal-title":"CACTI 6 0 A Tool to Model Large Caches","year":"2009","author":"muralimanohar","key":"24"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1145\/1594835.1504207"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1145\/1542275.1542303"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2005.13"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.1994.81"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736030"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.20"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/SUPERC.1988.44670"},{"key":"1","article-title":"Optimizing compilers for modern architectures","author":"allen","year":"2002","journal-title":"Morgan Kaufmann"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.50"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1145\/1356058.1356074"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/2259016.2259028"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1002\/spe.950"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522341"},{"key":"4","doi-asserted-by":"crossref","DOI":"10.1145\/232973.232983","article-title":"Memory bandwidth limitations of future microprocessors","author":"burger","year":"1996","journal-title":"ISCA"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1145\/1400112.1400113"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/232973.233002"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/292540.292554"},{"key":"19","doi-asserted-by":"crossref","DOI":"10.1145\/2333660.2333722","article-title":"XIOSim: Powerperformance modeling of mobile x86 cores","author":"kanev","year":"2012","journal-title":"ISLPED"},{"key":"17","article-title":"Synthesis lectures on computer architecture","author":"enright jerger","year":"2009","journal-title":"Morgan &Claypool"},{"key":"18","doi-asserted-by":"crossref","DOI":"10.1145\/1229428.1229474","article-title":"Speculative thread decomposition through empirical optimization","author":"johnson","year":"2007","journal-title":"PPoPP"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/40.848474"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/1772954.1772973"},{"key":"13","article-title":"Practical and accurate low-level pointer analysis","author":"guo","year":"2005","journal-title":"CGO"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/1054907.1054913"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCL.1992.185463"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378782"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919638"},{"key":"20","doi-asserted-by":"crossref","DOI":"10.1145\/1122971.1122997","article-title":"POSH: A TLS compiler that exploits program structure","author":"liu","year":"2006","journal-title":"PPoPP"},{"key":"49","article-title":"Uncovering hidden loop level parallelism in sequential applications","author":"zhong","year":"2008","journal-title":"HPCA"},{"key":"48","doi-asserted-by":"publisher","DOI":"10.1145\/1369396.1369399"},{"key":"45","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854322"},{"key":"44","doi-asserted-by":"publisher","DOI":"10.1145\/1945023.1945033"},{"key":"47","doi-asserted-by":"crossref","DOI":"10.1145\/605397.605416","article-title":"Compiler optimization of scalar value communication between speculative threads","author":"zhai","year":"2002","journal-title":"ASPLOS"},{"key":"46","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378780"},{"key":"10","article-title":"DOACROSS: Beyond vectorization for multiprocessors","author":"cytron","year":"1986","journal-title":"ICPP"}],"event":{"name":"2014 ACM\/IEEE 41st International Symposium on Computer Architecture (ISCA)","start":{"date-parts":[[2014,6,14]]},"location":"Minneapolis, MN, USA","end":{"date-parts":[[2014,6,18]]}},"container-title":["2014 ACM\/IEEE 41st International Symposium on Computer Architecture (ISCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6847316\/6853187\/06853215.pdf?arnumber=6853215","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,5,31]],"date-time":"2024-05-31T15:48:27Z","timestamp":1717170507000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6853215\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6]]},"references-count":49,"URL":"https:\/\/doi.org\/10.1109\/isca.2014.6853215","relation":{},"subject":[],"published":{"date-parts":[[2014,6]]}}}