{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:05:39Z","timestamp":1759147539272,"version":"3.28.0"},"reference-count":35,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,6]]},"DOI":"10.1109\/isca.2014.6853220","type":"proceedings-article","created":{"date-parts":[[2014,7,29]],"date-time":"2014-07-29T15:19:17Z","timestamp":1406647157000},"page":"385-396","source":"Crossref","is-referenced-by-count":7,"title":["Increasing off-chip bandwidth in multi-core processors with switchable pins"],"prefix":"10.1109","author":[{"given":"Shaoming","family":"Chen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yue","family":"Hu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ying","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lu","family":"Peng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jesse","family":"Ardonne","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Samuel","family":"Irving","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ashok","family":"Srivastava","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","article-title":"McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures","author":"li","year":"2009","journal-title":"Micro"},{"key":"35","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771792"},{"key":"17","first-page":"3","article-title":"A case for exploiting subarray-Ievel parallelism (SALP) in DRAM. SIGARCH Comput","volume":"40","author":"kim","year":"2012","journal-title":"Archit News"},{"journal-title":"VLSI Design","year":"2009","author":"kishore","key":"18"},{"key":"33","first-page":"3","article-title":"BOOM: Enabling mobile memory based low-power server DIMMs. SIGARCH Comput","volume":"40","author":"hyun yoon","year":"2012","journal-title":"NEWS Archive"},{"key":"15","article-title":"Self optimizing memory controllers : A reinforcement learning approach","author":"ipek","year":"2008","journal-title":"Proceedings of ISCA"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555788"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-7871-4"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.22"},{"key":"14","article-title":"Effective stream-based and execution-based data prefetching","volume":"4","author":"lacobovici","year":"2004","journal-title":"Proceedings of ICS"},{"journal-title":"Coordinating Processor and Main Memory for EffiCIent Server Power Control","year":"2011","author":"chen","key":"11"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.1994.367660"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237004"},{"key":"20","article-title":"Scalable power control for many-core architectures runmng multi-threaded applications","author":"ma","year":"2011","journal-title":"Proceedings of ISCA 2011"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2009.46"},{"journal-title":"Micron Corp Micron 2 Gb X 4 x8 xI6","year":"2011","key":"23"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.21"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.7"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.5"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555801"},{"journal-title":"Standard Performance Evaluation Corporation","year":"2006","key":"28"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379244"},{"year":"0","key":"3"},{"year":"0","key":"2"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"year":"0","key":"1"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2010.5560342"},{"year":"0","key":"7"},{"year":"0","key":"6"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815983"},{"year":"0","key":"5"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485955"},{"year":"0","key":"4"},{"journal-title":"Coordinated Management of Multiple Interacting Resources in Chip MUltiprocessors A Machine Learnmg Approach ln MICRO","year":"2008","author":"bitirgen","key":"9"},{"key":"8","article-title":"Future scalIng of processormemory interfaces","author":"ahn","year":"2009","journal-title":"Conf on High Performance Networking and Computing"}],"event":{"name":"2014 ACM\/IEEE 41st International Symposium on Computer Architecture (ISCA)","start":{"date-parts":[[2014,6,14]]},"location":"Minneapolis, MN, USA","end":{"date-parts":[[2014,6,18]]}},"container-title":["2014 ACM\/IEEE 41st International Symposium on Computer Architecture (ISCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6847316\/6853187\/06853220.pdf?arnumber=6853220","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T15:55:58Z","timestamp":1490284558000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6853220\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6]]},"references-count":35,"URL":"https:\/\/doi.org\/10.1109\/isca.2014.6853220","relation":{},"subject":[],"published":{"date-parts":[[2014,6]]}}}