{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,31]],"date-time":"2026-03-31T13:52:11Z","timestamp":1774965131778,"version":"3.50.1"},"reference-count":41,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,6]]},"DOI":"10.1109\/isca.2014.6853230","type":"proceedings-article","created":{"date-parts":[[2014,7,29]],"date-time":"2014-07-29T19:19:17Z","timestamp":1406661557000},"page":"337-348","source":"Crossref","is-referenced-by-count":18,"title":["Row-buffer decoupling: A case for low-latency DRAM microarchitecture"],"prefix":"10.1109","author":[{"given":"O.","family":"Seongil","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Young Hoon","family":"Son","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nam Sung","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jung Ho","family":"Ahn","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","year":"2013","journal-title":"Graphics Double Data Rate (GDDR5) SGRAM Standard"},{"key":"35","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"17","author":"jacob","year":"2007","journal-title":"Memory Systems Cache DRAM Disk"},{"key":"36","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379244"},{"key":"18","year":"2012","journal-title":"DDR4 SDRAM Specification"},{"key":"33","article-title":"GAGE: A critical evaluation of genome assemblies and assembly algorithms","author":"salzberg","year":"2011","journal-title":"Genome Research"},{"key":"15","year":"2010","journal-title":"Inte Processor 7500 Series Datasheet"},{"key":"34","article-title":"Samsung electronics","year":"2012","journal-title":"2GB DDR3 SDRAM Datasheet"},{"key":"16","article-title":"Self-optimizing memory controllers: A reinforcement learning approach","author":"ipek","year":"2008","journal-title":"ISCA"},{"key":"39","doi-asserted-by":"publisher","DOI":"10.1109\/4.962297"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.91"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2002.1015077"},{"key":"37","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485955"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/1241601.1241618"},{"key":"38","doi-asserted-by":"publisher","DOI":"10.1109\/4.962294"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/40.52944"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155624"},{"key":"20","doi-asserted-by":"crossref","DOI":"10.1145\/325164.325162","article-title":"Improving direct-mapped cache performance by the addition of a small fully-Associative cache and prefetch buffers","author":"jouppi","year":"1990","journal-title":"ISCA"},{"key":"41","article-title":"New generation of predictive technology model for sub-45nm design exploration","author":"zhao","year":"2006","journal-title":"ISQED"},{"key":"40","doi-asserted-by":"crossref","first-page":"24","DOI":"10.1109\/ISCA.1995.524546","article-title":"The SPLASH-2 programs: characterization and methodological considerations","author":"woo","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"22","article-title":"ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers","author":"kim","year":"2010","journal-title":"HPCA"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.51"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237032"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522354"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1145\/2445572.2445577"},{"key":"27","article-title":"Memory bandwidth and machine balance in current high performance computers","author":"mccalpin","year":"1995","journal-title":"IEEE Computer Society Technical Committee on Computer Architecture (TCCA) Newsletter"},{"key":"28","article-title":"Micron technology inc","year":"2011","journal-title":"Mobile LPDDR2 SDRAM Datasheet"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168945"},{"key":"3","first-page":"282","article-title":"Piranha: a scalable architecture based on single-chip multiprocessing","author":"barroso","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"2","article-title":"Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems","author":"ausavarungnirun","year":"2012","journal-title":"ISCA"},{"key":"10","article-title":"Multiple sub-row buffers in dram: Unlocking performance and energy improvement opportunities","author":"gulur","year":"2012","journal-title":"ICS"},{"key":"1","article-title":"McSimA+: A Manycore Simulator with Application-level+ Simulation and Detailed Microarchitecture Modeling","author":"ahn","year":"2013","journal-title":"ISPASS Apr"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.7"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2011.5762716"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/40.888701"},{"key":"32","first-page":"128","article-title":"Memory access scheduling","author":"rixner","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"31","article-title":"Hybrid memory cube","author":"pawlowski","year":"2011","journal-title":"Hot Chips"},{"key":"4","article-title":"Re-Architecting dram memory systems with monolithically integrated silicon photonics","author":"beamer","year":"2010","journal-title":"ISCA"},{"key":"9","author":"gealow","year":"1990","journal-title":"Impact of Processing Technology on DRAM Sense Amplifier Design"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/2094114.2094126"}],"event":{"name":"2014 ACM\/IEEE 41st International Symposium on Computer Architecture (ISCA)","location":"Minneapolis, MN","start":{"date-parts":[[2014,6,14]]},"end":{"date-parts":[[2014,6,18]]}},"container-title":["2014 ACM\/IEEE 41st International Symposium on Computer Architecture (ISCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6847316\/6853187\/06853230.pdf?arnumber=6853230","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,7,15]],"date-time":"2023-07-15T15:43:41Z","timestamp":1689435821000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6853230\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6]]},"references-count":41,"URL":"https:\/\/doi.org\/10.1109\/isca.2014.6853230","relation":{},"subject":[],"published":{"date-parts":[[2014,6]]}}}