{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,14]],"date-time":"2026-04-14T15:58:25Z","timestamp":1776182305309,"version":"3.50.1"},"reference-count":31,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,6]]},"DOI":"10.1109\/isca.2014.6853232","type":"proceedings-article","created":{"date-parts":[[2014,7,29]],"date-time":"2014-07-29T15:19:17Z","timestamp":1406647157000},"page":"25-36","source":"Crossref","is-referenced-by-count":27,"title":["SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering"],"prefix":"10.1109","author":[{"given":"Bhavya K.","family":"Daya","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chia-Hsin Owen","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Suvinay","family":"Subramanian","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Woo-Cheol","family":"Kwon","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sunghyun","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tushar","family":"Krishna","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jim","family":"Holt","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anantha P.","family":"Chandrakasan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Li-Shiuan","family":"Peh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2010.5647666"},{"key":"17","article-title":"A 48-core ia-32 message-passing processor with dvfs in 45nm cmos","author":"howard","year":"2010","journal-title":"ISSCC"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.40"},{"key":"15","article-title":"Parallel computer architecture","author":"culler","year":"1999","journal-title":"A Hardware\/Software Approach Morgan Kaufmann"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378782"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.96"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.43"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798238"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854332"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601881"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1145\/378993.378998"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1145\/859639.859640"},{"key":"24","doi-asserted-by":"crossref","DOI":"10.1145\/1105734.1105747","article-title":"Multifacets general execution-driven multiprocessor simulator (gems) toolset","author":"martin","year":"2005","journal-title":"Computer Architecture News"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416635"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.42"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228431"},{"key":"28","author":"sewell","year":"0","journal-title":"Scaling High-performance Interconnect Architectures to Many-core Systems"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.37"},{"key":"3","year":"0","journal-title":"Intel Xeon Processor E7 Family"},{"key":"2","year":"0","journal-title":"ARM AMBA"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669143"},{"key":"1","year":"0","journal-title":"AMD Opteron 6200 Series Processors"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"},{"key":"7","year":"2008"},{"key":"6","year":"0","journal-title":"Wind River Simics"},{"key":"5","year":"0","journal-title":"SPLASH-2"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378780"},{"key":"4","year":"0","journal-title":"Oracles SPARC T5-2 SPARC T5-4 SPARC T5-8 and SPARC T5-1B Server Architecture"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919636"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1988.5238"}],"event":{"name":"2014 ACM\/IEEE 41st International Symposium on Computer Architecture (ISCA)","location":"Minneapolis, MN, USA","start":{"date-parts":[[2014,6,14]]},"end":{"date-parts":[[2014,6,18]]}},"container-title":["2014 ACM\/IEEE 41st International Symposium on Computer Architecture (ISCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6847316\/6853187\/06853232.pdf?arnumber=6853232","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T13:30:57Z","timestamp":1498138257000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6853232\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6]]},"references-count":31,"URL":"https:\/\/doi.org\/10.1109\/isca.2014.6853232","relation":{},"subject":[],"published":{"date-parts":[[2014,6]]}}}