{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,29]],"date-time":"2025-12-29T22:23:41Z","timestamp":1767047021090,"version":"build-2065373602"},"reference-count":51,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,6]]},"DOI":"10.1109\/isca.2014.6853236","type":"proceedings-article","created":{"date-parts":[[2014,7,29]],"date-time":"2014-07-29T19:19:17Z","timestamp":1406661557000},"page":"109-120","source":"Crossref","is-referenced-by-count":17,"title":["SynFull: Synthetic traffic models capturing cache coherent behaviour"],"prefix":"10.1109","author":[{"given":"Mario","family":"Badr","sequence":"first","affiliation":[]},{"given":"Natalie Enright","family":"Jerger","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"35","doi-asserted-by":"publisher","DOI":"10.1016\/0377-0427(87)90125-7"},{"key":"36","doi-asserted-by":"publisher","DOI":"10.1109\/ICTAI.2004.50"},{"key":"33","article-title":"HORNET: A cycle-level multicore simulator","volume":"31","author":"ren","year":"2012","journal-title":"IEEE Trans Comput-Aided Design Integr Circuits Syst"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1007\/s10852-005-9022-1"},{"key":"39","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"37","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485963"},{"key":"38","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2001.953283"},{"key":"43","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815999"},{"key":"42","doi-asserted-by":"publisher","DOI":"10.1145\/360860.360863"},{"key":"41","doi-asserted-by":"publisher","DOI":"10.1109\/MASCOTS.2006.9"},{"key":"40","doi-asserted-by":"publisher","DOI":"10.2200\/S00346ED1V01Y201104CAC016"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1145\/1028176.1006729"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.29"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2002.8"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155630"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.14"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168953"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1145\/2209249.2209269"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416635"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169042"},{"key":"2","first-page":"22","article-title":"A generic traffic model for on-chip interconnection networks","author":"bahn","year":"2008","journal-title":"Network-on- Chip Architectures"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522340"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488779"},{"key":"7","first-page":"52","article-title":"Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation","author":"carlson","year":"2011","journal-title":"Proc Supercomput (SC)"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1080\/03610927408827101"},{"key":"32","doi-asserted-by":"crossref","DOI":"10.1145\/1999946.1999969","article-title":"FIST: A fast, lightweight, FPGA-friendly packet latency estimator for NoC modeling in fullsystem simulations","author":"papamichael","year":"2011","journal-title":"Proc Int Symp Networks-on-Chip"},{"journal-title":"Benchmarking Modern Multiprocessors","year":"2011","author":"bienia","key":"5"},{"key":"31","article-title":"FeS2: A full-system execution-driven simulator for x86","author":"neelakantam","year":"2008","journal-title":"Poster Presented at ASPLOS"},{"key":"4","doi-asserted-by":"crossref","DOI":"10.1515\/9781400874668","author":"bellman","year":"1961","journal-title":"Adaptive Control Processes A Guided Tour"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.47"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557141"},{"key":"19","doi-asserted-by":"crossref","DOI":"10.1109\/ISPASS.2013.6557149","article-title":"A detailed and flexible cycle-Accurate networkon-chip simulator","author":"jiang","year":"2013","journal-title":"Proc Int l Symp Performance Analysis of Systems and Software"},{"key":"17","article-title":"Automatic generation of miniaturized synthetic proxies for target applications to efficiently design multicore processors","volume":"99","author":"ganesan","year":"2013","journal-title":"IEEE Trans on Computers"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/1921249.1921258"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749726"},{"key":"16","volume":"12","author":"ferrari","year":"1984","journal-title":"On the Foundations of Artificial Workload Design ACM"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815976"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2000.842273"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.36"},{"journal-title":"Principles and Practices of Interconnec-tion Networks","year":"2003","author":"dally","key":"12"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2006.302734"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2011.164"},{"key":"49","doi-asserted-by":"publisher","DOI":"10.1145\/859626.859629"},{"key":"48","doi-asserted-by":"crossref","first-page":"24","DOI":"10.1109\/ISCA.1995.524546","article-title":"The SPLASH-2 programs: characterization and methodological considerations","author":"woo","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"45","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.820523"},{"key":"44","doi-asserted-by":"publisher","DOI":"10.1145\/1150343.1150364"},{"key":"47","doi-asserted-by":"publisher","DOI":"10.1080\/01621459.1963.10500845"},{"key":"46","doi-asserted-by":"publisher","DOI":"10.3844\/jcssp.2010.363.368"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/2019608.2019609"},{"key":"51","first-page":"218","article-title":"Analyzing the impact of on-chip network traffic on program phases for CMPs","author":"zhang","year":"2009","journal-title":"Intl Symp on Performance Analysis of Systems and Software"},{"key":"50","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669166"}],"event":{"name":"2014 ACM\/IEEE 41st International Symposium on Computer Architecture (ISCA)","start":{"date-parts":[[2014,6,14]]},"location":"Minneapolis, MN, USA","end":{"date-parts":[[2014,6,18]]}},"container-title":["2014 ACM\/IEEE 41st International Symposium on Computer Architecture (ISCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6847316\/6853187\/06853236.pdf?arnumber=6853236","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,7,15]],"date-time":"2023-07-15T15:43:45Z","timestamp":1689435825000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6853236\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6]]},"references-count":51,"URL":"https:\/\/doi.org\/10.1109\/isca.2014.6853236","relation":{},"subject":[],"published":{"date-parts":[[2014,6]]}}}