{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,6]],"date-time":"2024-08-06T05:43:33Z","timestamp":1722923013847},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iscas.2002.1010496","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T20:42:54Z","timestamp":1056573774000},"page":"IV-477-IV-480","source":"Crossref","is-referenced-by-count":2,"title":["A self-checking cell logic block for fault tolerant FPGAs"],"prefix":"10.1109","volume":"4","author":[{"given":"S.","family":"Pontarelli","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.C.","family":"Cardarilli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Leandri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Ottavi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Re","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Salsano","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/APASIC.1999.824101"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.2000.903403"},{"key":"ref10","first-page":"948","article-title":"CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults","author":"metra","year":"1992","journal-title":"IEEE International Test Conference"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2000.887167"},{"key":"ref11","article-title":"System-on-Chip Implementation and Fault-Coverage Estimation of a Fault-Tolerant State Machine","author":"cardarilli","year":"2001","journal-title":"7th International Conference on Information Systems Analysis and Synthesis (ISAS 2001)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.1999.802890"},{"journal-title":"Testability of Electronic Circuits","year":"1992","author":"weyerer","key":"ref12"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1995.529816"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1994.315652"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.1999.802900"},{"key":"ref9","first-page":"303","article-title":"A practical current sensing technique for IDDQ testing","author":"tang","year":"1995","journal-title":"IEEE Transaction on VLSI"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/92.678870"}],"event":{"name":"2002 IEEE International Symposium on Circuits and Systems","acronym":"ISCAS-02","location":"Phoenix-Scottsdale, AZ, USA"},"container-title":["2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/7897\/21779\/01010496.pdf?arnumber=1010496","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,10]],"date-time":"2017-03-10T18:49:12Z","timestamp":1489171752000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1010496\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/iscas.2002.1010496","relation":{},"subject":[]}}