{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:52:10Z","timestamp":1759146730382},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iscas.2002.1010556","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T16:42:54Z","timestamp":1056559374000},"page":"IV-711-IV-714","source":"Crossref","is-referenced-by-count":11,"title":["A design methodology for IP integration"],"prefix":"10.1109","volume":"4","author":[{"given":"P.","family":"Coussy","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Baganne","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Martin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/82.673640"},{"article-title":"High-level synthesis Introduction to Chip and System Design","year":"1992","author":"gajski","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-2649-7"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-2887-3"},{"key":"ref4","article-title":"Interface-Based Design","author":"rowson","year":"1997","journal-title":"Proc of DAC"},{"key":"ref3","article-title":"VS1 abandons plans for system-chip bus","author":"cataldo","year":"1997","journal-title":"EETimes"},{"key":"ref6","article-title":"CoWare A design environment for heterogeneous hw\/sw systems","author":"van rompaey","year":"1996","journal-title":"Proc of EuroDAC"},{"key":"ref5","article-title":"Techniques for reducing Read latency of Core Bus Wrapper","author":"lysescky","year":"2000","journal-title":"Proc of DATE"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"8","DOI":"10.1145\/277044.277047","article-title":"Automatic synthesis of interfaces between incompatible protocols","author":"passerone","year":"1998","journal-title":"Proceedings 1998 Design and Automation Conference 35th DAC (Cat No 98CH36175) DAC"},{"journal-title":"Cadence VCC","year":"2001","key":"ref7"},{"journal-title":"Virtual Socket Interface Alliance","year":"0","key":"ref2"},{"journal-title":"Inventra","year":"0","key":"ref1"},{"key":"ref9","article-title":"Synthesis of communication Interfaces for SOC using VSIA recommendation","author":"cyr","year":"2001","journal-title":"Proc of DATE"}],"event":{"name":"2002 IEEE International Symposium on Circuits and Systems","acronym":"ISCAS-02","location":"Phoenix-Scottsdale, AZ, USA"},"container-title":["2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/7897\/21779\/01010556.pdf?arnumber=1010556","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T18:40:02Z","timestamp":1497552002000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1010556\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/iscas.2002.1010556","relation":{},"subject":[]}}