{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,15]],"date-time":"2025-04-15T06:11:41Z","timestamp":1744697501219},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iscas.2002.1010747","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T20:42:54Z","timestamp":1056573774000},"page":"V-489-V-492","source":"Crossref","is-referenced-by-count":31,"title":["Accurate programming of analog floating-gate arrays"],"prefix":"10.1109","volume":"5","author":[{"given":"P.D.","family":"Smith","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Kucic","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Hasler","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","article-title":"An autozeroing floating&#x2013;gate amplifier","author":"hasler","year":"2000","journal-title":"IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/82.913181"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/82.913187"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/82.913191"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/ARVLSI.1999.756050"},{"key":"ref8","first-page":"10017","author":"brown","year":"1998","journal-title":"Nonvolatile Semi-conductor Memory Technology A Comprehensive Guide to Understanding and Using NVSM Devices"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/ISCAS.1999.780747"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/ARVLSI.2001.915557"},{"key":"ref9","first-page":"817","article-title":"Single transistor learning synapses","author":"paul","year":"1995","journal-title":"Advances in Neural Information Processing Systems 7"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1002\/j.1538-7305.1967.tb01738.x"}],"event":{"acronym":"ISCAS-02","name":"2002 IEEE International Symposium on Circuits and Systems","location":"Phoenix-Scottsdale, AZ, USA"},"container-title":["2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/7897\/21767\/01010747.pdf?arnumber=1010747","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,10]],"date-time":"2017-03-10T23:25:19Z","timestamp":1489188319000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1010747\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/iscas.2002.1010747","relation":{},"subject":[]}}